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11.发明申请PAGE BUFFER, MEMORY DEVICE COMPRISING PAGE BUFFER, AND RELATED METHOD OF OPERATION 有权页面缓冲器，包含页面缓冲器的存储器件以及相关的操作方法公开(公告)号：US20130250678A1
公开(公告)日：2013-09-26
申请号：US13718105
申请日：2012-12-18
发明人： Sang-Hyun Joo , Il-Han Park , Ki-Hwan Song
CPC分类号： G11C11/24 , G11C16/02 , G11C16/10 , G11C2216/14
摘要： A page buffer comprises a static latch configured to store data received from an external device, and a dynamic latch configured to receive the data stored in the static latch through a floating node, the dynamic latch comprising a storage capacitor, a write transistor configured to write the data of the floating node to the storage capacitor, and a read transistor configured to read the data of the storage capacitor, and the write transistor and the read transistor sharing the floating node.
摘要翻译： 页面缓冲器包括被配置为存储从外部设备接收的数据的静态锁存器和配置成通过浮动节点接收存储在静态锁存器中的数据的动态锁存器，该动态锁存器包括存储电容器，写入晶体管被配置为写入 浮动节点到存储电容器的数据，以及被配置为读取存储电容器的数据的读取晶体管，以及共享浮动节点的写入晶体管和读取晶体管。
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12.发明授权公开(公告)号：US11961564B2
公开(公告)日：2024-04-16
申请号：US17503952
申请日：2021-10-18
发明人： Chang-Yeon Yu , Kui-Han Ko , Il-Han Park , June-Hong Park , Joo-Yong Park , Joon-Young Park , Bong-Soon Lim
CPC分类号： G11C16/102 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/0483
摘要： To program in a nonvolatile memory device including a cell region including first metal pads and a peripheral region including second metal pads and vertically connected to the cell region by the first metal pads and the second metal pads, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.
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13.发明授权公开(公告)号：US11183249B2
公开(公告)日：2021-11-23
申请号：US16141147
申请日：2018-09-25
发明人： Chang-Yeon Yu , Kui-Han Ko , Il-Han Park , June-Hong Park , Joo-Yong Park , Joon-Young Park , Bong-Soon Lim
IPC分类号： G11C16/16 , G11C16/08 , G11C16/26 , G11C16/04 , G11C16/24 , G11C11/56 , G11C16/10 , H01L27/11556 , H01L27/1157 , H01L27/11582
摘要： To program in a nonvolatile memory device, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.
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公开(公告)号：US09543026B2
公开(公告)日：2017-01-10
申请号：US14865275
申请日：2015-09-25
发明人： Jung-Ho Song , Minsu Kim , Il-Han Park , Su Chang Jeon
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/32 , G11C16/3459 , G11C2207/005
摘要： An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer.
摘要翻译： 提供了一种非易失性存储器件的操作方法。 非易失性存储器件分别包括第一和第二页缓冲器以及与其相连的第一和第二位线。 第一页缓冲器的第一和第二锁存节点被充电以具有根据存储在第一页缓冲器的第一锁存器中的数据具有第一电平的电压。 在第一锁存节点的充电开始之后，第二页缓冲器的感测节点被预充电。 感测节点连接到第二位线。 存储在第一锁存器中的数据在第二页缓冲器的感测节点的预充电期间被转储到第一页缓冲器的第二锁存器中。
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公开(公告)号：US20160093388A1
公开(公告)日：2016-03-31
申请号：US14865275
申请日：2015-09-25
发明人： JUNG-HO SONG , Minsu Kim , Il-Han Park , Su Chang Jeon
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/32 , G11C16/3459 , G11C2207/005
摘要： An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer.
摘要翻译： 提供了一种非易失性存储器件的操作方法。 非易失性存储器件分别包括第一和第二页缓冲器以及与其相连的第一和第二位线。 第一页缓冲器的第一和第二锁存节点被充电以具有根据存储在第一页缓冲器的第一锁存器中的数据具有第一电平的电压。 在第一锁存节点的充电开始之后，第二页缓冲器的感测节点被预充电。 感测节点连接到第二位线。 存储在第一锁存器中的数据在第二页缓冲器的感测节点的预充电期间被转储到第一页缓冲器的第二锁存器中。
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公开(公告)号：US20190318784A1
公开(公告)日：2019-10-17
申请号：US16213420
申请日：2018-12-07
发明人： Kang-Bin Lee , Il-Han Park , Jong-Hoo Jo
摘要： In a method of programming in a nonvolatile memory device, channels of a plurality of cell strings are precharged through ground selection transistors by a precharge voltage of a source line. A turn-on voltage is applied to a selected ground selection transistor of a selected cell string among the plurality of cell strings, during a verification read period of an N-th program loop. The turn-on voltage applied to the selected ground selection transistor is maintained to precharge the channels for an (N+1)-th program loop, without recovery after the verification read period of the N-th program loop is finished. Power consumption is reduced and an operation speed is increased by maintaining the turn-on voltage of the selected ground selection line to precharge the channels of the cell strings without recovery after the verification read operation is finished.
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17.发明授权公开(公告)号：US10332607B2
公开(公告)日：2019-06-25
申请号：US15830679
申请日：2017-12-04
发明人： Na-Young Choi , Il-Han Park , Seung-Hwan Song
IPC分类号： G11C16/34 , G11C16/28 , G11C16/08 , G06F11/10 , G11C16/24 , G11C29/02 , G11C29/42 , G11C11/56 , G11C29/52 , G11C16/04
摘要： In a method of operating a nonvolatile memory device including a memory cell array, where the memory cell array includes a plurality of pages, and each of the plurality of pages includes a plurality of nonvolatile memory cells, a first sampling read operation is performed to count a first number of memory cells in a first region of a first page selected from the plurality of pages, using a first default read voltage and a first offset read voltage, and a second sampling read operation is selectively performed to count a second number of memory cells in a second region of the first page, using the first default read voltage and a second offset read voltage, based on a comparison result of the first number and a first reference value. The second offset read voltage is different from the first offset read voltage.
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18.发明申请公开(公告)号：US20180261296A1
公开(公告)日：2018-09-13
申请号：US15830679
申请日：2017-12-04
发明人： NA-YOUNG CHOI , Il-Han Park , Seung-Hwan Song
CPC分类号： G11C16/3431 , G06F11/1068 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/28 , G11C16/3427 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/52 , G11C2211/5642
摘要： In a method of operating a nonvolatile memory device including a memory cell array, where the memory cell array includes a plurality of pages, and each of the plurality of pages includes a plurality of nonvolatile memory cells, a first sampling read operation is performed to count a first number of memory cells in a first region of a first page selected from the plurality of pages, using a first default read voltage and a first offset read voltage, and a second sampling read operation is selectively performed to count a second number of memory cells in a second region of the first page, using the first default read voltage and a second offset read voltage, based on a comparison result of the first number and a first reference value. The second offset read voltage is different from the first offset read voltage.
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公开(公告)号：US08982618B2
公开(公告)日：2015-03-17
申请号：US13795750
申请日：2013-03-12
发明人： Sang-Hyun Joo , Il-Han Park , Ki-Whan Song
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/06 , G11C16/10 , G11C16/26
摘要： A nonvolatile memory device comprises a nonvolatile memory chip comprising a static latch, first and second dynamic latches that receive the data stored in the static latch through a floating node, and a memory cell configured to store multi-bit data. The nonvolatile memory device performs a refresh operation on the first dynamic latch where externally supplied first single bit data is stored in the first dynamic latch, performs a refresh operation on the second dynamic latch where externally supplied second single bit data is stored in the second dynamic latch, and programs the memory cell using the data stored in the first and second dynamic latches after the first and second single bit data are stored in the respective first and second dynamic latches.
摘要翻译： 非易失性存储器件包括非易失性存储器芯片，其包括静态锁存器，通过浮动节点接收存储在静态锁存器中的数据的第一和第二动态锁存器以及被配置为存储多位数据的存储器单元。 非易失性存储器件对第一动态锁存器执行刷新操作，其中外部提供的第一单位数据被存储在第一动态锁存器中，对外部提供的第二单位数据存储在第二动态锁存器中的第二动态锁存器执行刷新操作 在第一和第二单个位数据存储在相应的第一和第二动态锁存器中之后，使用存储在第一和第二动态锁存器中的数据对存储器单元进行锁存和编程。
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