公开(公告)号：US09490216B2

公开(公告)日：2016-11-08

申请号：US14596480

申请日：2015-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Jin Moon ,  Tae-Seong Kim ,  Byung-Lyul Park ,  Jae-Hwa Park ,  Suk-Chul Bang

IPC: H01L23/522 ,  H01L23/544 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/544 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/522 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a semiconductor package. The semiconductor device includes semiconductor device includes a semiconductor substrate having a first side and a second side. A front-side structure including an internal circuit is disposed on the first side of the semiconductor substrate. A passivation layer is disposed on the second side of the semiconductor substrate. A through-via structure passes through the semiconductor substrate and the passivation layer. A back-side conductive pattern is disposed on the second side of the semiconductor substrate. The back-side conductive pattern is electrically connected to the through-via structure. An alignment recessed area is disposed in the passivation layer. An insulating alignment pattern is disposed in the alignment recessed area.

Abstract translation: 提供半导体器件和半导体封装。 半导体器件包括半导体器件，其包括具有第一侧和第二侧的半导体衬底。 包括内部电路的前侧结构设置在半导体衬底的第一侧上。 钝化层设置在半导体衬底的第二侧上。 通孔结构通过半导体衬底和钝化层。 背面导电图案设置在半导体衬底的第二侧上。 背面导电图案电连接到通孔结构。 在钝化层中设置对准凹陷区域。 绝缘对准图案设置在对准凹陷区域中。

公开(公告)号：US08860221B2

公开(公告)日：2014-10-14

申请号：US13685174

申请日：2012-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kun-Sang Park ,  Byung-Lyul Park ,  Su-Kyoung Kim ,  Kwang-Jin Moon ,  Suk-Chul Bang ,  Do-Sun Lee ,  Dong-Chan Lim ,  Gil-Heyun Choi

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/28 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0655 ,  H01L2224/05009 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/0903 ,  H01L2224/8001 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: Provided are electrode-connecting structures or semiconductor devices, including a lower device including a lower substrate, a lower insulating layer formed on the lower substrate, and a lower electrode structure formed in the lower insulating layer, wherein the lower electrode structure includes a lower electrode barrier layer and a lower metal electrode formed on the lower electrode barrier layer, and an upper device including an upper substrate, an upper insulating layer formed under the upper substrate, and an upper electrode structure formed in the upper insulating layer, wherein the upper electrode structure includes an upper electrode barrier layer extending from the inside of the upper insulating layer under a bottom surface thereof and an upper metal electrode formed on the upper electrode barrier layer. The lower metal electrode is in direct contact with the upper metal electrode.

Abstract translation: 提供了电极连接结构或半导体器件，包括下部器件，包括下部衬底，形成在下部衬底上的下部绝缘层和形成在下部绝缘层中的下部电极结构，其中下部电极结构包括下部电极 阻挡层和形成在下电极阻挡层上的下金属电极，以及上装置，包括上基板，形成在上基板下的上绝缘层和形成在上绝缘层中的上电极结构，上电极 结构包括从其下表面上的上绝缘层的内部延伸的上电极阻挡层和形成在上电极阻挡层上的上金属电极。 下部金属电极与上部金属电极直接接触。

公开(公告)号：US11600552B2

公开(公告)日：2023-03-07

申请号：US17344138

申请日：2021-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Bin Seo ,  Su-Jeong Park ,  Tae-Seong Kim ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Ju-Il Choi

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L27/146 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.

公开(公告)号：US20210296211A1

公开(公告)日：2021-09-23

申请号：US17344138

申请日：2021-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Bin SEO ,  Su-Jeong Park ,  Tae-Seong Kim ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Ju-Il Choi

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/31 ,  H01L27/146

Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.

公开(公告)号：US11094612B2

公开(公告)日：2021-08-17

申请号：US15936019

申请日：2018-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Kwang-Jin Moon ,  Byung-Lyul Park ,  Jin-Ho An ,  Atsushi Fujisaki

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure.

公开(公告)号：US10950578B2

公开(公告)日：2021-03-16

申请号：US16430625

申请日：2019-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Seung Lee ,  Kwang-Jin Moon ,  Tae-Seong Kim ,  Dae-Suk Lee ,  Dong-Chan Lim

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.

公开(公告)号：US20210183822A1

公开(公告)日：2021-06-17

申请号：US17190113

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Seung LEE ,  Kwang-Jin Moon ,  Tae-Seong Kim ,  Dae-Suk Lee ,  Dong-Chan Lim

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.

公开(公告)号：US20200161277A1

公开(公告)日：2020-05-21

申请号：US16430625

申请日：2019-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Seung LEE ,  Kwang-Jin Moon ,  Tae-Seong Kim ,  Dae-Suk Lee ,  Dong-Chan Lim

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.

公开(公告)号：US10580726B2

公开(公告)日：2020-03-03

申请号：US16106645

申请日：2018-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Ho Chun ,  Seong-Min Son ,  Hyung-Jun Jeon ,  Kwang-Jin Moon ,  Jin-Ho An ,  Ho-Jin Lee ,  Atsushi Fujisaki

IPC: H01L23/498 ,  H01L23/525 ,  H01L23/532 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

Abstract: A semiconductor device and a method of manufacturing the same, the device including a through-hole electrode structure extending through a substrate; a redistribution layer on the through-hole electrode structure; and a conductive pad, the conductive pad including a penetrating portion extending through the redistribution layer; and a protrusion portion on the penetrating portion, the protrusion portion protruding from an upper surface of the redistribution layer, wherein a central region of an upper surface of the protrusion portion is flat and not closer to the substrate than an edge region of the upper surface of the protrusion portion.

公开(公告)号：US20170062308A1

公开(公告)日：2017-03-02

申请号：US15151079

申请日：2016-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-ll Choi ,  Hyo-Ju Kim ,  Yeun-Sang Park ,  Atsushi Fujisaki ,  Kwang-Jin Moon ,  Byung-Lyul Park

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/481 ,  H01L21/486 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0501 ,  H01L2924/05032 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.

Abstract translation: 一种半导体器件包括穿透衬底的通孔结构，所述通孔结构的一部分在所述衬底的表面上暴露，所述保护层图案结构设置在所述衬底的表面上并且包括第一保护层图案和第二保护 所述第一保护层图案围绕所述通孔结构的所述暴露部分的下侧壁并暴露所述通孔结构的所述暴露部分的上侧壁，所述第二保护层图案暴露所述第一保护的顶表面的一部分 所述衬垫结构设置在所述通孔结构和所述保护层图案结构上并且覆盖由所述第二保护层图案暴露的所述第一保护层图案的顶表面。