公开(公告)号：US20240281323A1

公开(公告)日：2024-08-22

申请号：US18469894

申请日：2023-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungkyu Lee ,  Seongmuk Kang ,  Jiho Kim ,  Kijun Lee ,  Kyomin Sohn

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: A memory controller including a processor and configured to control a memory module including a plurality of data chips and at least one parity chip includes an error correction code (ECC) engine, the ECC engine including an ECC decoder to correct Q symbols errors in a codeword set read from the memory module, Q is a maximum natural number equal to or less than P and P is a natural number equal to or greater than four. The ECC decoder is configured to generate a syndrome including first through P-th syndrome symbols based on the read codeword set by using a parity check matrix and to perform a first ECC decoding to correct a single symbol error in the read codeword set based on the first syndrome symbol and a selected syndrome symbol corresponding to one of the second through P-th syndrome symbols.

公开(公告)号：US20240161850A1

公开(公告)日：2024-05-16

申请号：US18362130

申请日：2023-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byeongho Kim ,  Shinhaeng Kang ,  Suk Han Lee ,  Hweesoo Kim ,  Kyomin Sohn

IPC: G11C29/18 ,  G11C29/12

CPC classification number: G11C29/18 ,  G11C29/1201 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit performing a read operation on data stored in the plurality of memory banks based on a first command and a first address received from a host. When a PIM instruction set is stored before the first command and the first address are received, the logic circuit is configured to perform a PIM command execution operation. When an error associated with the PIM command execution operation occurs, the logic circuit is configured to generate error data and record the error data at the log register through the first channels. The logic circuit is configured to output event data indicating an existence of the error data to the host in a first operation mode. The logic circuit is configured to output the error data to the host in a second operation mode.

公开(公告)号：US11860803B2

公开(公告)日：2024-01-02

申请号：US17685987

申请日：2022-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Jaeyoun Youn

IPC: G06F13/38 ,  G06F13/16 ,  H01L25/065 ,  G11C8/10 ,  G11C7/10

CPC classification number: G06F13/1668 ,  H01L25/0657 ,  G11C7/10 ,  G11C8/10 ,  H01L2225/06541

Abstract: A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.

公开(公告)号：US11763876B2

公开(公告)日：2023-09-19

申请号：US17475479

申请日：2021-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Seongil O ,  Haesuk Lee

IPC: G11C8/12 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/4087 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/40618

Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.

公开(公告)号：US11620504B2

公开(公告)日：2023-04-04

申请号：US16892637

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-Soo Yu ,  Nam Sung Kim ,  Kyomin Sohn ,  Jaeyoun Youn

IPC: G06N3/063 ,  G06N3/08 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/54 ,  G11C11/56

Abstract: A neuromorphic device includes a memory cell array that includes first memory cells corresponding to a first address and storing first weights and second memory cells corresponding to a second address and storing second weights, and a neuron circuit that includes an integrator summing first read signals from the first memory cells and an activation circuit outputting a first activation signal based on a first sum signal of the first read signals output from the integrator.

公开(公告)号：US11158357B2

公开(公告)日：2021-10-26

申请号：US16813851

申请日：2020-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Soo Yu ,  Namsung Kim ,  Kyomin Sohn ,  Seongil O ,  Sukhan Lee

IPC: G11C7/10 ,  G11C11/40 ,  G11C5/02 ,  G11C11/408 ,  G11C11/409

Abstract: A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.

公开(公告)号：US11127713B2

公开(公告)日：2021-09-21

申请号：US16926189

申请日：2020-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Kyomin Sohn ,  Jaeyoun Youn

IPC: H01L25/065 ,  H01L23/538 ,  H01L21/66

Abstract: High bandwidth memories and systems including the same may include a buffer die, a plurality of memory dies stacked on the buffer die, a plurality of dummy bump groups in edge regions of the buffer die and the plurality of memory dies, and a plurality of signal line groups. Each of the plurality of dummy bump groups includes dummy bumps spaced apart from each other between each pair of adjacent dies and configured to connect the two adjacent dies to each other. Each of the signal line groups includes a plurality of signal lines configured to transmit a corresponding signal among an input signal and a plurality of bump crack detection signals applied to an input dummy bump of each of the plurality of dummy bump groups via sequential transmission through the plurality of dummy bumps to an output dummy bump during a bump crack test operation.

公开(公告)号：US10784184B2

公开(公告)日：2020-09-22

申请号：US16263408

申请日：2019-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Rho ,  Chisung Oh ,  Kyomin Sohn ,  Yong-Ki Kim ,  Jong-Ho Moon ,  SeungHan Woo ,  Jaeyoun Youn

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/528 ,  H01L23/522 ,  H01L25/065

Abstract: A semiconductor device includes first to M-th semiconductor dies stacked in a first direction. Each of the first to M-th semiconductor dies includes a substrate, first to K-th through silicon vias passing through the substrate in the first direction, and a first circuit to receive power through a power supply line electrically connected to the first through silicon via. Each of first to K-th through silicon vias of the N-th semiconductor die is electrically connected to a through silicon via of first to K-th through silicon vias of the (N+1)-th semiconductor die that is spaced apart therefrom in a plan view.

公开(公告)号：US20240347524A1

公开(公告)日：2024-10-17

申请号：US18403022

申请日：2024-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Kyomin Sohn ,  Duksung Kim ,  Byoungkon Jo ,  Jangseok Choi

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/18 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/16 ,  H01L25/50 ,  H10B80/00 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/80357 ,  H01L2224/94 ,  H01L2924/1436

Abstract: A semiconductor package according to an example embodiment of the present disclosure includes: a package substrate; and first to third memory dies disposed on the package substrate and sequentially stacked in a first direction, perpendicular to an upper surface of the package substrate, and the first memory die and the second memory die are attached to each other without a bump, and the second memory die and the third memory die are attached to each other by a plurality of bumps.

公开(公告)号：US20240233798A9

公开(公告)日：2024-07-11

申请号：US18327335

申请日：2023-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho ,  Kyomin Sohn ,  Kijun Lee

IPC: G11C11/406 ,  G06F12/02

CPC classification number: G11C11/406 ,  G06F12/0223

Abstract: A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.