公开(公告)号：US09666551B1

公开(公告)日：2017-05-30

申请号：US15236814

申请日：2016-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Seung-kwan Ryu ,  Cha-jea Jo ,  Tae-Je Cho

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L24/14 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1415 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.

公开(公告)号：US20170084558A1

公开(公告)日：2017-03-23

申请号：US15226231

申请日：2016-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Tae-je Cho ,  Yong-hwan Kwon ,  Hyung-gil Baek ,  Hyun-soo Chung ,  Seung-kwan Ryu ,  Myeong-soon Park

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L24/08 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/08058 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/19105 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/034 ,  H01L2224/1146 ,  H01L2224/0361 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01024 ,  H01L2924/01022

Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.

公开(公告)号：US20150102485A1

公开(公告)日：2015-04-16

申请号：US14288997

申请日：2014-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-byoung Kang ,  Kyung-wook Paik ,  Tae-Je Cho ,  Young-kun Jee ,  Sun-kyoung Seo ,  Yong-won Choi ,  Ji-won Shin

IPC: H01L23/29 ,  H01L23/538 ,  C08K3/08 ,  H01L23/50

CPC classification number: C08K3/08 ,  C08K2003/0893 ,  C08K2201/011 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/17181 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/2929 ,  H01L2224/29318 ,  H01L2224/32505 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/8211

Abstract: A non-conductive material layer, selected from a non-conductive film and a non-conductive polymer paste, and containing a dispersion of zinc (Zn) particles is disclosed, together with semiconductor packages including the non-conductive material layer. The non-conductive material layer contains zinc (Zn) particles having an average particle diameter of about 1 nm to about 200 nm in a non-conductive polymer base material of a film type, and a semiconductor package includes the non-conductive film. By using the non-conductive film and/or the non-conductive paste containing the zinc dispersion, e a semiconductor package having excellent electric connection properties and high reliability may be manufactured through simple processes at low manufacturing costs.

Abstract translation: 公开了一种选自非导电膜和非导电聚合物浆料并含有锌（Zn）颗粒的分散体的非导电材料层以及包括非导电材料层的半导体封装。 非导电材料层在薄膜型非导电性聚合物基材中含有平均粒径为约1nm〜约200nm的锌（Zn）颗粒，半导体封装包括非导电膜。 通过使用含有锌分散体的非导电性膜和/或非导电性糊剂，可以以低制造成本通过简单的工艺制造具有优异的电连接性能和高可靠性的半导体封装。