公开(公告)号：US10056433B2

公开(公告)日：2018-08-21

申请号：US15231616

申请日：2016-08-08

Applicant: Toshiba Memory Corporation

Inventor： Masahiro Kiyotoshi ,  Akihito Yamamoto ,  Yoshio Ozawa ,  Fumitaka Arai ,  Riichiro Shirota

IPC: H01L21/70 ,  H01L27/24 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L45/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/51

CPC classification number: H01L27/249 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/762 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2436 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1633

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

公开(公告)号：US09984754B2

公开(公告)日：2018-05-29

申请号：US14645708

申请日：2015-03-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Wataru Sakamoto ,  Fumitaka Arai ,  Tatsuya Kato

IPC: G11C16/10 ,  G11C16/04 ,  H01L27/115 ,  G11C11/56 ,  H01L27/11524 ,  H01L27/11556

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556

Abstract: According to an embodiment, an operation method for a memory device which has a first memory element and a second memory element respectively provided on both sides of a semiconductor member includes applying a first potential on the second word line to write a second data to the second memory and applying a second potential on the first word line to write the first data to the first memory. The first potential increases by a first step voltage and the second potential increases by a second step voltage.

公开(公告)号：US20180097011A1

公开(公告)日：2018-04-05

申请号：US15819003

申请日：2017-11-21

Applicant: Toshiba Memory Corporation

Inventor： Koichi Sakata ,  Yuta Watanabe ,  Keisuke Kikutani ,  Satoshi Nagashima ,  Fumitaka Arai ,  Toshiyuki Iwamoto

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11565 ,  H01L21/311

Abstract: A semiconductor memory device according to one embodiment, includes a first electrode film, a plurality of semiconductor members, and a charge storage member. The first electrode film includes three or more first portions and a second portion connecting the first portions to each other. The first portions extend in a first direction and are arranged along a second direction that intersects with the first direction. The plurality of semiconductor members are arranged along the first direction between the first portions and extending in a third direction. The third direction intersects with a plane containing the first direction and the second direction. The charge storage member is disposed between each of the semiconductor members and each of the first portions. The second portion is disposed between the semiconductor members.

公开(公告)号：US10991713B2

公开(公告)日：2021-04-27

申请号：US16298865

申请日：2019-03-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi Nagashima ,  Keisuke Nakatsuka ,  Fumitaka Arai ,  Shinya Arai ,  Yasuhiro Uchiyama

IPC: H01L27/11578 ,  G11C11/40 ,  H01L27/1157

Abstract: According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.

公开(公告)号：US10686045B2

公开(公告)日：2020-06-16

申请号：US15683941

申请日：2017-08-23

Applicant: Toshiba Memory Corporation

Inventor： Tatsuya Kato ,  Fumitaka Arai ,  Katsuyuki Sekine ,  Toshiyuki Iwamoto ,  Yuta Watanabe ,  Wataru Sakamoto

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/788

Abstract: A semiconductor memory device according to an embodiment, includes a pair of first electrodes, a semiconductor pillar, an inter-pillar insulating member, a first insulating film, a second electrode, and a second insulating film. The pair of first electrodes are separated from each other, and extend in a first direction. The semiconductor pillar and the inter-pillar insulating member are arranged alternately along the first direction between the pair of first electrodes. The semiconductor pillar and the inter-pillar insulating member extend in a second direction crossing the first direction. The first insulating film is provided at a periphery of the semiconductor pillar. The second electrode is provided between the first insulating film and each electrode of the pair of first electrodes. The second electrode is not provided between the semiconductor pillar and the inter-pillar insulating member. The second insulating film is provided between the second electrode and the first electrode.

公开(公告)号：US20180301461A1

公开(公告)日：2018-10-18

申请号：US16012285

申请日：2018-06-19

Applicant: Toshiba Memory Corporation

Inventor： Tatsuya Kato ,  Atsushi Murakoshi ,  Fumitaka Arai

IPC: H01L27/11521 ,  H01L27/11556

CPC classification number: H01L27/11521 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556

Abstract: A semiconductor memory device includes a first electrode film and a second electrode film spreading along a first direction and a second direction, first insulating plates intermittently disposed along the first direction and each of two columns separated in the second direction from each other, second insulating plates provided between the two columns, intermittently disposed along the first direction and each of n columns, third insulating plates provided between one of the two columns and a column formed of the second insulating plates, intermittently disposed along the first direction, a first insulating member provided between the first insulating plate and the third insulating plate, and a second insulating member provided between the second insulating plate and the third insulating plate. The first electrode film is divided into two parts between the two columns. The second electrode film is divided into {(n+1)×2} parts between the two columns.

公开(公告)号：US20180269210A1

公开(公告)日：2018-09-20

申请号：US15704643

申请日：2017-09-14

Applicant: Toshiba Memory Corporation

Inventor： Tsutomu TEZUKA ,  Fumitaka Arai ,  Keiji Ikeda ,  Tomomasa Ueda ,  Nobuyoshi Saito ,  Chika Tanaka ,  Kentaro Miura

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/10802 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26 ,  H01L27/10847 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.

公开(公告)号：US10043808B1

公开(公告)日：2018-08-07

申请号：US15705457

申请日：2017-09-15

Applicant: Toshiba Memory Corporation

Inventor： Tsutomu Tezuka ,  Fumitaka Arai ,  Keiji Ikeda ,  Tomomasa Ueda ,  Nobuyoshi Saito ,  Chika Tanaka ,  Kentaro Miura

IPC: H01L29/76 ,  H01L27/105 ,  H01L29/792 ,  H01L29/786 ,  G11C11/4097 ,  H01L29/423

Abstract: According to one embodiment, a semiconductor memory includes: a first gate of a first select transistor and a second gate of a second select transistor on a gate insulating film on a semiconductor layer; an oxide semiconductor layer above the semiconductor layer; a first control gate of a first cell and a second control gate of a second cell on an insulating layer on the oxide semiconductor layer; a third gate of a first transistor between the first control gate and the second control gate; a fourth gate of a second transistor between a first end of the oxide semiconductor layer and the second control gate; an interconnect connected to the first end; a source line connected to the first select transistor; and a bit line connected to the second select transistor.

公开(公告)号：US20170352735A1

公开(公告)日：2017-12-07

申请号：US15683941

申请日：2017-08-23

Applicant: Toshiba Memory Corporation

Inventor： Tatsuya Kato ,  Fumitaka Arai ,  Katsuyuki Sekine ,  Toshiyuke Iwamoto ,  Yuta Watanabe ,  Wataru Sakamoto

IPC: H01L29/423 ,  H01L27/11556 ,  H01L27/11524 ,  H01L29/788 ,  H01L21/28

Abstract: A semiconductor memory device according to an embodiment, includes a pair of first electrodes, a semiconductor pillar, an inter-pillar insulating member, a first insulating film, a second electrode, and a second insulating film. The pair of first electrodes are separated from each other, and extend in a first direction. The semiconductor pillar and the inter-pillar insulating member are arranged alternately along the first direction between the pair of first electrodes. The semiconductor pillar and the inter-pillar insulating member extend in a second direction crossing the first direction. The first insulating film is provided at a periphery of the semiconductor pillar. The second electrode is provided between the first insulating film and each electrode of the pair of first electrodes. The second electrode is not provided between the semiconductor pillar and the inter-pillar insulating member. The second insulating film is provided between the second electrode and the first electrode.

公开(公告)号：US11107508B2

公开(公告)日：2021-08-31

申请号：US16562372

申请日：2019-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiji Hosotani ,  Fumitaka Arai ,  Keisuke Nakatsuka

IPC: H01L27/11578 ,  G11C5/06 ,  H01L23/48 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  G11C16/30 ,  H01L27/11556 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11524

Abstract: According to one embodiment, a semiconductor memory device includes: a conductive layer including a first portion and a second portion electrically coupled to the first portion; a first contact plug electrically coupled to the first portion; a first semiconductor layer; a first insulating layer between the second portion and the first semiconductor layer, and between the first portion and the first semiconductor layer; a second contact plug coupled to the first semiconductor layer in a region in which the first insulating layer is formed; a first interconnect; and a first memory cell apart from the second portion in the second direction and storing information between the first semiconductor layer and the first interconnect.