公开(公告)号：US20200273773A1

公开(公告)日：2020-08-27

申请号：US16283852

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chao-Wen Shih ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Sen-Kuei Hsu

IPC: H01L23/373 ,  H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q1/02

Abstract: A semiconductor device including a chip package and an antenna package disposed on the chip package is provided. The chip package includes a semiconductor chip, an encapsulation enclosing the semiconductor chip, and a redistribution structure disposed on the semiconductor chip and the encapsulation and electrically coupled to the semiconductor chip. The antenna package includes an antenna pattern electrically coupled to the chip package, and an intermediate structure disposed between the antenna pattern and the chip package, wherein the intermediate structure comprises a ceramic element in contact with the redistribution structure and thermally dissipating a heat generated from the semiconductor chip.

公开(公告)号：US20200153083A1

公开(公告)日：2020-05-14

申请号：US16740464

申请日：2020-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Chien Hsiao ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chao-Wen Shih ,  Shou-Zen Chang

IPC: H01Q1/22 ,  H01Q25/00 ,  H01Q19/06 ,  H01Q9/04 ,  H01Q1/24 ,  H01L23/31 ,  H01L21/56 ,  H01L23/66 ,  H01L23/498 ,  H01L21/683

Abstract: In accordance with some embodiments, a package structure includes an RFIC chip. an insulating encapsulation, a redistribution circuit structure, an antenna and a microwave director. The insulating encapsulation encapsulates the RFIC chip. The redistribution circuit structure is disposed on the insulating encapsulation and electrically connected to the RFIC chip. The antenna is disposed on the insulating encapsulation and electrically connected to the RFIC chip through the redistribution circuit structure. The antenna is located between the microwave director and the RFIC chip. The microwave director has a microwave directivity enhancement surface located at a propagating path of a microwave received or generated by the antenna.

公开(公告)号：US20200067173A1

公开(公告)日：2020-02-27

申请号：US16671182

申请日：2019-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Nan-Chin Chuang ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chao-Wen Shih ,  Shou-Zen Chang

IPC: H01Q1/22 ,  H01L23/31 ,  H01Q21/24 ,  H01Q21/00 ,  H01L23/552 ,  H01L23/00 ,  H01L23/66 ,  H01Q1/52 ,  H01Q19/30

Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.

公开(公告)号：US10483617B2

公开(公告)日：2019-11-19

申请号：US15879456

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Nan-Chin Chuang ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chao-Wen Shih ,  Shou-Zen Chang

IPC: H01Q1/22 ,  H01L23/66 ,  H01L23/31 ,  H01L23/00 ,  H01L23/552 ,  H01Q21/00 ,  H01Q21/24 ,  H01Q1/52 ,  H01Q19/30 ,  H01Q15/14 ,  H01Q21/28

Abstract: A package structure including an insulating encapsulation, at least one semiconductor die, at least one first antenna and at least one second antenna is provided. The insulating encapsulation includes a first portion, a second portion and a third portion, wherein the second portion is located between the first portion and the third portion. The at least one semiconductor die is encapsulated in the first portion of the insulating encapsulation, and the second portion and the third portion are stacked on the at least one semiconductor die. The at least one first antenna is electrically connected to the at least one semiconductor die and encapsulated in the third portion of the insulating encapsulation. The at least one second antenna is electrically connected to the at least one semiconductor die and encapsulated in the second portion of the insulating encapsulation.

公开(公告)号：US20190252762A1

公开(公告)日：2019-08-15

申请号：US16396769

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Chien Hsiao ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chao-Wen Shih ,  Shou-Zen Chang

IPC: H01Q1/22 ,  H01L23/31 ,  H01L21/56 ,  H01L23/66 ,  H01Q25/00 ,  H01Q1/24 ,  H01Q9/04 ,  H01Q19/06 ,  H01L23/498

Abstract: In accordance with some embodiments, a package structure includes an RFIC chip. an insulating encapsulation, a redistribution circuit structure, an antenna and a microwave director. The insulating encapsulation encapsulates the RFIC chip. The redistribution circuit structure is disposed on the insulating encapsulation and electrically connected to the RFIC chip. The antenna is disposed on the insulating encapsulation and electrically connected to the RFIC chip through the redistribution circuit structure. The antenna is located between the microwave director and the RFIC chip. The microwave director has a microwave directivity enhancement surface located at a propagating path of a microwave received or generated by the antenna.

公开(公告)号：US20240387452A1

公开(公告)日：2024-11-21

申请号：US18785335

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/306 ,  H01L21/768 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

公开(公告)号：US12125819B2

公开(公告)日：2024-10-22

申请号：US17883999

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/304 ,  H01L21/306

CPC classification number: H01L24/94 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/76898 ,  H01L24/06 ,  H01L24/33 ,  H01L2224/03845 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/27831 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29005 ,  H01L2224/29011 ,  H01L2224/29016 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/83203 ,  H01L2224/83896 ,  H01L2224/9211 ,  H01L2225/06544

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

公开(公告)号：US11894299B2

公开(公告)日：2024-02-06

申请号：US17188787

申请日：2021-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Wen Shih ,  Chen-Hua Yu ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Sen-Kuei Hsu

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/525 ,  H01L21/56 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/5225 ,  H01L23/5329 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76885 ,  H01L23/5286 ,  H01L24/13 ,  H01L2224/0348 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/11622 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16104 ,  H01L2224/03462 ,  H01L2924/00014

Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

公开(公告)号：US20230378012A1

公开(公告)日：2023-11-23

申请号：US17896840

申请日：2022-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Min-Chien Hsiao ,  Chun-Chiang Kuo ,  Tsung-Shu Lin

IPC: H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/3192 ,  H01L21/568 ,  H01L23/3185 ,  H01L25/0655 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/20 ,  H01L25/105 ,  H01L24/19 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L24/06 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/80201 ,  H01L2224/80896 ,  H01L2224/211 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1041 ,  H01L2224/19

Abstract: In an embodiment, a device includes: a first integrated circuit die; a second integrated circuit die; a gap-fill dielectric between a first sidewall of the first integrated circuit die and a second sidewall of the second integrated circuit die; a protective cap overlapping the gap-fill dielectric, the first sidewall of the first integrated circuit die, and the second sidewall of the second integrated circuit die; and an isolation layer around the protective cap, the isolation layer disposed on the first integrated circuit die, and the second integrated circuit die.

公开(公告)号：US11705409B2

公开(公告)日：2023-07-18

申请号：US16916066

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chao-Wen Shih ,  Han-Ping Pu ,  Meng-Tse Chen ,  Sheng-Hsiang Chiu

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/66 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/5226 ,  H01L2223/6677

Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.