公开(公告)号：US10361139B2

公开(公告)日：2019-07-23

申请号：US15884397

申请日：2018-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Tseng ,  Hung-Jui Kuo ,  Ming-Che Ho ,  Chia-Hung Liu

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package includes an encapsulated semiconductor device, a redistribution structure, and a protection layer. The encapsulated semiconductor device includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. The redistribution structure is disposed on the encapsulated semiconductor device and includes a dielectric layer and a redistribution circuit layer electrically connected to the semiconductor device. The protection layer at least covers the dielectric layer, wherein an oxygen permeability or a water vapor permeability of the protection layer is substantially lower than an oxygen permeability or a vapor permeability of the dielectric layer.

公开(公告)号：US10297544B2

公开(公告)日：2019-05-21

申请号：US15716476

申请日：2017-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L21/768

Abstract: Provided is an integrated fan-out package including a die, an insulating encapsulation, a redistribution circuit structure, a conductive terminal, and a barrier layer. The die is encapsulated by the insulating encapsulation. The redistribution circuit structure includes a redistribution conductive layer. The redistribution conductive layer is disposed in the insulating encapsulation and extending from a first surface of the insulating encapsulation to a second surface of the insulating encapsulation. The conductive terminal is disposed over the second surface of the insulating encapsulation. The barrier layer is sandwiched between the redistribution conductive layer and the conductive terminal. A material of the barrier layer is different from a material of the redistribution conductive layer and a material of the conductive terminal. A method of fabricating the integrated fan-out package is also provided.

公开(公告)号：US20240178091A1

公开(公告)日：2024-05-30

申请号：US18435362

申请日：2024-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/16 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/3157 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76843 ,  H01L23/16 ,  H01L23/5226 ,  H01L23/528

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US11935804B2

公开(公告)日：2024-03-19

申请号：US18297927

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/16 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/3157 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76843 ,  H01L23/16 ,  H01L23/5226 ,  H01L23/528

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US11495506B2

公开(公告)日：2022-11-08

申请号：US16835146

申请日：2020-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Tseng ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: G11C5/06 ,  H01L27/108 ,  H01L21/02 ,  H01L21/56 ,  H01L21/762 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a first integrated circuit structure, a first encapsulation material laterally encapsulating the first integrated circuit structure, a first redistribution structure, a solder layer, a second integrated circuit structure, a second encapsulation material second laterally encapsulating the second integrated circuit structure and a second redistribution structure. The first integrated circuit structure includes a first metallization layer. The first redistribution structure is disposed over the first integrated circuit structure and first encapsulation material. The first metallization layer faces away from the first redistribution structure and thermally coupled to the first redistribution structure. The solder layer is dispose over the first redistribution structure. The second integrated circuit structure is disposed on the first redistribution structure and includes a second metallization layer in contact with the solder layer. The second redistribution structure is disposed over the second integrated circuit structure and the second encapsulation material.

公开(公告)号：US20210020559A1

公开(公告)日：2021-01-21

申请号：US16513727

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tuan-Yu Hung ,  Ching-Feng Yang ,  Hung-Jui Kuo ,  Kai-Chiang Wu ,  Ming-Che Ho

IPC: H01L23/498 ,  H01L23/00 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/28 ,  H01L21/768 ,  H01L21/56 ,  H01L23/66 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, a through via structure, a dipole structure and an encapsulant. The through via structure and the dipole structure are disposed aside the semiconductor die, and respectively includes an insulating core and a conductive layer. A front surface and a sidewall of the insulating core are covered by the conductive layer. The semiconductor die, the through via structure and the dipole structure are laterally encapsulated by the encapsulant. Surfaces of capping portions of the conductive layers covering the front surfaces of the insulating cores are substantially coplanar with a front surface of the encapsulant.

公开(公告)号：US20200273805A1

公开(公告)日：2020-08-27

申请号：US16283836

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/532 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768

Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first dielectric layer, a first conductive pattern and a barrier layer. The first conductive pattern is disposed in a second dielectric layer over the first dielectric layer. The barrier layer is disposed at an interface between the first conductive pattern and the second dielectric layer and an interface between the first dielectric layer and the second dielectric layer.

公开(公告)号：US10163832B1

公开(公告)日：2018-12-25

申请号：US15795281

申请日：2017-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yun Huang ,  Ming-Che Ho

IPC: H01L23/00 ,  H01L25/16

Abstract: A redistribution circuit structure electrically connected to a die underneath is provided. The redistribution circuit structure includes a dielectric layer and a conductive layer. The dielectric layer partially covers the die, so that a conductive pillar of the die is exposed by the dielectric layer. The conductive layer is disposed over the dielectric layer and electrically connected to the die by the conductive pillar. The conductive layer includes a multilayer structure, wherein an average grain size of one layer of the multilayer structure is less than or equal to 2 μm. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.

公开(公告)号：US09899342B2

公开(公告)日：2018-02-20

申请号：US15164888

申请日：2016-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Hui Lee ,  Hung-Jui Kuo ,  Ming-Che Ho ,  Tzu-Yun Huang

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/11015 ,  H01L2224/12105 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2924/014

Abstract: A redistribution circuit structure electrically connected to at least one conductor underneath is provided. The redistribution circuit structure includes a dielectric layer, an alignment, and a redistribution conductive layer. The dielectric layer covers the conductor and includes at least one contact opening for exposing the conductor. The alignment mark is disposed on the dielectric layer. The alignment mark includes a base portion on the dielectric layer and a protruding portion on the base portion, wherein a ratio of a maximum thickness of the protruding portion to a thickness of the base portion is smaller than 25%. The redistribution conductive layer is disposed on the dielectric layer. The redistribution conductive layer includes a conductive via, and the conductive via is electrically connected to the conductor through the contact opening. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.

公开(公告)号：US11842955B2

公开(公告)日：2023-12-12

申请号：US17852766

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hung-Jui Kuo ,  Ming-Che Ho ,  Tzung-Hui Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/48 ,  H01L23/485 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/485 ,  H01L24/19 ,  H01L24/20 ,  H01L24/83 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/83815 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.