公开(公告)号：US09851780B2

公开(公告)日：2017-12-26

申请号：US14829644

申请日：2015-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: G06F1/32 ,  G06F3/06 ,  H01L27/10 ,  H01L27/06 ,  H01L27/07 ,  H01L27/108 ,  G11C16/00 ,  G11C7/10 ,  G11C5/14

CPC classification number: G06F1/3293 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G11C5/141 ,  G11C7/1006 ,  G11C16/00 ,  G11C2211/4016 ,  H01L27/06 ,  H01L27/07 ,  H01L27/108

Abstract: A semiconductor device includes a main processor, a normally-off processor, and at least one oxide semiconductor random access memory (RAM). The normally-off processor includes at least one oxide semiconductor transistor. The main processor is connected to the normally-off processor, and a clock rate of the main processor is higher than a clock rate of the normally-off processor. The oxide semiconductor RAM is connected to the normally-off processor. An operating method of the semiconductor includes backing up data from the main processor to the normally-off processor and/or the oxide semiconductor RAM.

公开(公告)号：US09728454B1

公开(公告)日：2017-08-08

申请号：US15242611

申请日：2016-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Xing Hua Zhang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234

CPC classification number: H01L21/76895 ,  H01L21/7681 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823475

Abstract: The present invention provides a semiconductor structure, includes a substrate, a dielectric layer disposed on the substrate, a first gate structure and a second gate structure disposed in the dielectric layer, a hard mask disposed in the dielectric layer, where the hard mask covers a sidewall of the first gate structure, and covers the second gate structure, and a contact structure disposed in the dielectric layer. The contact structure at least crosses over the hard mask. The contact structure includes a first contact portion and a second contact portion. The first contact portion contacts the first gate structure directly, the second contact portion contacts the substrate directly, and the hard mask is disposed between the first contact portion and the second contact portion.

公开(公告)号：US11011649B2

公开(公告)日：2021-05-18

申请号：US16027386

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chen-Bin Lin ,  Ding-Lung Chen ,  Chi-Fa Ku

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L21/426 ,  H01L27/12 ,  H01L29/49

Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

公开(公告)号：US10727234B2

公开(公告)日：2020-07-28

申请号：US15361479

申请日：2016-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Xing Hua Zhang ,  Shan Liu ,  Runshun Wang ,  Chien-Fu Chen ,  Wei-Jen Wang ,  Chen-Hsien Hsu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/8238

Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.

公开(公告)号：US09935099B2

公开(公告)日：2018-04-03

申请号：US14956398

申请日：2015-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Chen-Bin Lin ,  Su Xing ,  Chi-Chang Shuai ,  Chung-Yuan Lee

IPC: H01L27/06 ,  H01L23/535 ,  H01L29/22 ,  H01L29/861 ,  H01L29/10 ,  H01L29/24 ,  H01L49/02 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L23/535 ,  H01L27/0727 ,  H01L28/00 ,  H01L28/40 ,  H01L29/0603 ,  H01L29/1079 ,  H01L29/22 ,  H01L29/24 ,  H01L29/861

Abstract: The present invention provides a semiconductor device including a semiconductor substrate, a first well, a second well, a gate electrode, an oxide semiconductor structure and a diode. The first well is disposed in the semiconductor substrate and has a first conductive type, and the second well is also disposed in the semiconductor substrate, adjacent to the first well, and has a second conductive type. The gate electrode is disposed on the first well. The oxide semiconductor structure is disposed on the semiconductor substrate and electrically connected to the second well. The diode is disposed between the first well and the second well.

公开(公告)号：US09887293B2

公开(公告)日：2018-02-06

申请号：US15191542

申请日：2016-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Chen-Bin Lin ,  Sanpo Wang ,  Chung-Yuan Lee ,  Chi-Fa Ku

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L29/78609 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions are disposed on the oxide-semiconductor layer. The first dielectric layer covers on the oxide-semiconductor layer and source/drain regions. A second gate electrode is disposed between source/drain regions and partially covers the oxide-semiconductor layer. The oxide-semiconductor layer may be optionally disposed between the first gate electrode and the oxide-semiconductor layer or be disposed on the second gate electrode.

公开(公告)号：US09847428B1

公开(公告)日：2017-12-19

申请号：US15230496

申请日：2016-08-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/78648 ,  H01L29/41733 ,  H01L29/7869 ,  H01L29/78696

Abstract: An oxide semiconductor device includes an oxide semiconductor transistor including a first gate electrode, a second gate electrode, a third gate electrode, a first oxide semiconductor channel layer, a second oxide semiconductor channel layer, and two source/drain electrodes. The second gate electrode is disposed above the first gate electrode. The third gate electrode is disposed above the second gate electrode. At least a part of the first oxide semiconductor channel layer is disposed between the first gate electrode and the second gate electrode. At least a part of the second oxide semiconductor channel layer is disposed between the second gate electrode and the third gate electrode. At least a part of each source/drain electrode is disposed between the first oxide semiconductor channel layer and the second oxide semiconductor channel layer. Each source/drain electrode contacts the first oxide semiconductor channel layer and the second oxide semiconductor channel layer.

公开(公告)号：US09666491B1

公开(公告)日：2017-05-30

申请号：US15185007

申请日：2016-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L21/8256 ,  H01L23/528 ,  H01L27/088 ,  H01L29/66 ,  H01L49/02 ,  H01L21/477 ,  H01L21/428 ,  H01L29/40

CPC classification number: H01L21/8256 ,  H01L21/428 ,  H01L21/477 ,  H01L21/8258 ,  H01L23/5283 ,  H01L24/19 ,  H01L27/0629 ,  H01L27/0694 ,  H01L27/088 ,  H01L28/40 ,  H01L29/401 ,  H01L29/66969

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a first transistor is formed on a first surface of a substrate. Next, a thinning process is performed on the second surface of the substrate which is opposite to the first surface, to form a third surface. Then, a second transistor is formed on the third surface, in which the second transistor and the first transistor are electrically connected to each other through a through-silicon via penetrating through the first surface and the third surface.

公开(公告)号：US09564217B1

公开(公告)日：2017-02-07

申请号：US14886116

申请日：2015-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Chen-Bin Lin ,  Chi-Fa Ku ,  Shao-Hui Wu

IPC: H01L27/10 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78 ,  G11C14/00 ,  H01L29/786 ,  H01L27/108 ,  H01L27/105

CPC classification number: G11C14/0009 ,  G11C14/0027 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L28/60

Abstract: A semiconductor memory device includes a semiconductor substrate having a main surface, at least a first dielectric layer on the main surface of the semiconductor substrate, a first OS FET device and a second OS FET device disposed on the first dielectric layer, at least a second dielectric layer covering the first dielectric layer, the first OS FET device, and the second OS FET device, a first MIM capacitor on the second dielectric layer and electrically coupled to the first OS FET device, and a second MIM capacitor on the second dielectric layer and electrically coupled to the second OS FET device.

Abstract translation: 半导体存储器件包括具有主表面的半导体衬底，在半导体衬底的主表面上的至少第一电介质层，设置在第一介电层上的第一OS FET器件和第二OS FET器件，至少第二 覆盖第一电介质层的介质层，第一OS FET器件和第二OS FET器件，第二介电层上的第一MIM电容器，并且电耦合到第一OS FET器件;以及第二MIM电容器， 并电耦合到第二OS FET器件。

公开(公告)号：US12038588B2

公开(公告)日：2024-07-16

申请号：US18236381

申请日：2023-08-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou

IPC: G02B27/01 ,  H01L25/075 ,  H01L33/62

CPC classification number: G02B27/0172 ,  H01L25/0753 ,  H01L33/62 ,  G02B2027/0178

Abstract: A method of manufacturing a layout structure of Micro LED for augmented reality and mixed reality is provided in the present invention, including steps of providing a substrate with multiple display units arranged thereon to form an unit array and includes an edge region and a transparent region surrounded by the edge region, forming pixel driver circuits and a first transparent layer on the edge region, setting multiple Micro LEDs on the first transparent layer of edge regions, forming a second transparent layer on the Micro LEDs and the first transparent layer, thinning and removing the substrate on the transparent region to expose the first transparent layer, and forming a protection layer on back sides of the substrate and the exposed first transparent layer.