公开(公告)号：US09575816B2

公开(公告)日：2017-02-21

申请号：US13758924

申请日：2013-02-04

Applicant: VIA Technologies, Inc.

Inventor： Rodney E. Hooker ,  Douglas R. Reed

IPC: G06F9/52 ,  G06F9/38 ,  G06F11/07

CPC classification number: G06F9/526 ,  G06F9/38 ,  G06F9/3836 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/0793

Abstract: A microprocessor includes a main processor and a service processor. The service processor is configured to detect and break a deadlock/livelock condition in the main processor. The service processor detects the deadlock/livelock condition by detecting the main processor has not retired an instruction or completed a processor bus transaction for a predetermined number of clock cycles. In response to detecting the deadlock/livelock condition in the main processor, the service processor causes arbitration requests to a cache memory to be captured in a buffer, analyzes the captured requests to detect a pattern that may indicate a bug causing the condition and performs actions associated with the pattern to break the deadlock/livelock. The actions include suppression of arbitration requests to the cache, suppression of comparisons cache request addresses and killing requests to access the cache.

Abstract translation: 微处理器包括主处理器和服务处理器。 服务处理器被配置为检测并破坏主处理器中的死锁/活动锁定状态。 服务处理器通过检测主处理器未停止指令或完成处理器总线事务达预定数量的时钟周期来检测死锁/活动锁定状况。 响应于检测到主处理器中的死锁/活动锁定状况，服务处理器将向高速缓冲存储器发出仲裁请求以在缓冲器中被捕获，分析所捕获的请求以检测可能指示导致条件的错误并执行动作的模式 与模式相关联以打破僵局/活锁。 这些操作包括抑制对缓存的仲裁请求，抑制比较缓存请求地址和杀死访问高速缓存的请求。

公开(公告)号：US09575778B2

公开(公告)日：2017-02-21

申请号：US14474699

申请日：2014-09-02

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Wen-Chi Chen ,  Rodney E. Hooker

IPC: G06F9/445 ,  G06F15/177 ,  G06F9/44

CPC classification number: G06F9/44505 ,  G06F9/448 ,  G06F15/177

Abstract: A system includes functional units that are dynamically configurable during operation of the system. The system also includes a first module that collects performance data while the system executes a program with the functional units configured according to a configuration setting. The system also includes a second module that sends information to a server. The information includes the performance data, the configuration setting and data from which the program may be identified. The system also includes a third module that instructs the system to re-configure the functional units with a new configuration setting received from the server while the program is being executed by the system. The new configuration setting is based on analysis by the server of the information sent by the system and of similar information sent by other systems that include the dynamically configurable functional units.

Abstract translation: 系统包括在系统运行期间可动态配置的功能单元。 系统还包括在系统执行程序时收集性能数据的第一模块，功能单元根据配置设置配置。 该系统还包括向服务器发送信息的第二个模块。 该信息包括性能数据，配置设置和可以识别程序的数据。 该系统还包括第三模块，其指示系统在系统执行程序时从服务器接收到的新配置设置来重新配置功能单元。 新的配置设置是基于服务器分析系统发送的信息以及其他系统发送的类似信息，包括动态配置的功能单元。

公开(公告)号：US09483406B2

公开(公告)日：2016-11-01

申请号：US14315064

申请日：2014-06-25

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  John Michael Greer

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/383 ,  G06F2212/502 ,  G06F2212/6026

Abstract: A microprocessor includes a first hardware data prefetcher that prefetches data into the microprocessor according to a first algorithm. The microprocessor also includes a second hardware data prefetcher that prefetches data into the microprocessor according to a second algorithm, wherein the first and second algorithms are different. The second prefetcher detects that it is prefetching data into the microprocessor according to the second algorithm in excess of a first predetermined rate and, in response, sends a throttle indication to the first prefetcher. The first prefetcher prefetches data into the microprocessor according to the first algorithm at below a second predetermined rate in response to receiving the throttle indication from the second prefetcher.

Abstract translation: 微处理器包括根据第一算法将数据预取到微处理器的第一硬件数据预取器。 微处理器还包括第二硬件数据预取器，其根据第二算法将数据预取到微处理器中，其中第一和第二算法是不同的。 第二预取器检测到根据第二算法将数据预取到微处理器中超过第一预定速率，并且作为响应，向第一预取器发送节气门指示。 响应于从第二预取器接收到节气门指示，第一预取器根据第一算法在低于第二预定速率的情况下将数据预取到微处理器中。

公开(公告)号：US20150089204A1

公开(公告)日：2015-03-26

申请号：US14050687

申请日：2013-10-10

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Rodney E. Hooker ,  Colin Eddy ,  Terry Parks

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F8/654 ,  G06F9/30181 ,  G06F15/7892 ,  G06F17/5054

Abstract: A microprocessor includes a plurality of dynamically reconfigurable functional units, a fingerprint, and a fingerprint unit. As the plurality of dynamically reconfigurable functional units execute instructions according to a first configuration setting, the fingerprint unit accumulates information about the instructions according to a mathematical operation to generate a result. The microprocessor also includes a reconfiguration unit that reconfigures the plurality of dynamically reconfigurable functional units to execute instructions according to a second configuration setting in response to an indication that the result matches the fingerprint.

Abstract translation: 微处理器包括多个动态可重构功能单元，指纹和指纹单元。 当多个动态可重构功能单元根据第一配置设置执行指令时，指纹单元根据数学运算累加关于指令的信息以产生结果。 微处理器还包括重配置单元，其重新配置多个动态可重配置功能单元，以响应于结果与指纹匹配的指示，根据第二配置设置来执行指令。

公开(公告)号：US08880807B2

公开(公告)日：2014-11-04

申请号：US14282420

申请日：2014-05-20

Applicant: VIA Technologies, Inc.

Inventor： Rodney E. Hooker ,  John Michael Greer

IPC: G06F12/00 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3814 ,  G06F12/0862 ,  G06F2212/602 ,  G06F2212/6026

Abstract: A data prefetcher in a microprocessor. The data prefetcher includes a plurality of period match counters associated with a corresponding plurality of different pattern periods. The data prefetcher also includes control logic that updates the plurality of period match counters in response to accesses to a memory block by the microprocessor, determines a clear pattern period based on the plurality of period match counters and prefetches into the microprocessor non-fetched cache lines within the memory block based on a pattern having the clear pattern period determined based on the plurality of period match counters.

Abstract translation: 微处理器中的数据预取器。 数据预取器包括与相应的多个不同模式周期相关联的多个周期匹配计数器。 数据预取器还包括响应于微处理器对存储器块的访问而更新多个周期匹配计数器的控制逻辑，基于多个周期匹配计数器确定清除模式周期，并预取到微处理器未获取的高速缓存行 基于具有基于多个周期匹配计数器确定的清除模式周期的模式在存储块内。

公开(公告)号：US20140289479A1

公开(公告)日：2014-09-25

申请号：US14282420

申请日：2014-05-20

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  John Michael Greer

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3814 ,  G06F12/0862 ,  G06F2212/602 ,  G06F2212/6026

Abstract: A data prefetcher in a microprocessor. The data prefetcher includes a plurality of period match counters associated with a corresponding plurality of different pattern periods. The data prefetcher also includes control logic that updates the plurality of period match counters in response to accesses to a memory block by the microprocessor, determines a clear pattern period based on the plurality of period match counters and prefetches into the microprocessor non-fetched cache lines within the memory block based on a pattern having the clear pattern period determined based on the plurality of period match counters.

Abstract translation: 微处理器中的数据预取器。 数据预取器包括与相应的多个不同模式周期相关联的多个周期匹配计数器。 数据预取器还包括响应于微处理器对存储器块的访问而更新多个周期匹配计数器的控制逻辑，基于多个周期匹配计数器确定清除模式周期，并预取到微处理器未获取的高速缓存行 基于具有基于多个周期匹配计数器确定的清除模式周期的模式在存储块内。

公开(公告)号：US09898291B2

公开(公告)日：2018-02-20

申请号：US14963134

申请日：2015-12-08

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

IPC: G06F9/30 ,  G06F12/0875 ,  G06F9/44

CPC classification number: G06F9/3016 ,  G06F9/30025 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/4401 ,  G06F12/0875 ,  G06F2212/452

Abstract: A microprocessor natively translates and executes instructions of both the x86 instruction set architecture (ISA) and the Advanced RISC Machines (ARM) ISA. An instruction formatter extracts distinct ARM instruction bytes from a stream of instruction bytes received from an instruction cache and formats them. ARM and x86 instruction length decoders decode ARM and x86 instruction bytes, respectively, and determine instruction lengths of ARM and x86 instructions. An instruction translator translates the formatted x86 ISA and ARM ISA instructions into microinstructions of a unified microinstruction set architecture of the microprocessor. An execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions.

公开(公告)号：US09891927B2

公开(公告)日：2018-02-13

申请号：US14281551

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Stephan Gaskins

IPC: G06F1/00 ,  H04L29/06 ,  G06F9/38 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F9/44 ,  G06F13/364 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0875 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  H04L9/08

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the plurality of processing cores. Each core of the plurality of processing cores comprises microcode run by the core that implements architectural instructions of an instruction set architecture of the microprocessor. The microcode is configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores.

公开(公告)号：US09317301B2

公开(公告)日：2016-04-19

申请号：US14526029

申请日：2014-10-28

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

IPC: G06F9/445 ,  G06F9/28 ,  G06F9/44 ,  G06F9/30 ,  G06F9/26 ,  G06F9/38 ,  G06F15/82

CPC classification number: G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

Abstract: A microprocessor includes a plurality of registers that holds an architectural state of the microprocessor and an indicator that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA. The microprocessor also includes a hardware instruction translator that translates x86 ISA instructions and ARM ISA instructions into microinstructions. The hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal. The microprocessor also includes an execution pipeline, coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. In response to the reset signal, the microprocessor initializes its architectural state in the plurality of registers as defined by the boot ISA prior to fetching the initial ISA instructions.

Abstract translation: 微处理器包括保持微处理器架构状态的多个寄存器和指示微处理器的引导指令集体系结构（ISA）作为x86 ISA或高级RISC机器（ARM）ISA的指示符。 微处理器还包括硬件指令转换器，将x86 ISA指令和ARM ISA指令转换为微指令。 作为引导ISA的指令，硬件指令转换器将转换为接收复位信号后微处理器从架构存储器空间中提取的初始ISA指令。 微处理器还包括耦合到硬件指令转换器的执行流水线。 执行流水线执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。 响应于复位信号，微处理器在获取初始ISA指令之前初始化由引导ISA定义的多个寄存器中的架构状态。

公开(公告)号：US20140310479A1

公开(公告)日：2014-10-16

申请号：US14315064

申请日：2014-06-25

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  John Michael Greer

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/383 ,  G06F2212/502 ,  G06F2212/6026

Abstract: A microprocessor includes a first hardware data prefetcher that prefetches data into the microprocessor according to a first algorithm. The microprocessor also includes a second hardware data prefetcher that prefetches data into the microprocessor according to a second algorithm, wherein the first and second algorithms are different. The second prefetcher detects that it is prefetching data into the microprocessor according to the second algorithm in excess of a first predetermined rate and, in response, sends a throttle indication to the first prefetcher. The first prefetcher prefetches data into the microprocessor according to the first algorithm at below a second predetermined rate in response to receiving the throttle indication from the second prefetcher.

Abstract translation: 微处理器包括根据第一算法将数据预取到微处理器的第一硬件数据预取器。 微处理器还包括第二硬件数据预取器，其根据第二算法将数据预取到微处理器中，其中第一和第二算法是不同的。 第二预取器检测到根据第二算法将数据预取到微处理器中超过第一预定速率，并且作为响应，向第一预取器发送节气门指示。 响应于从第二预取器接收到节气门指示，第一预取器根据第一算法在低于第二预定速率的情况下将数据预取到微处理器中。