公开(公告)号：US07087512B2

公开(公告)日：2006-08-08

申请号：US10642092

申请日：2003-08-15

申请人： Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

发明人： Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166

摘要： A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region, application of a corrodible metalization layer to the dielectric, application of a protection device to the metalization layer, and removal of the protection device in a region around the connection region.

公开(公告)号：US06826037B2

公开(公告)日：2004-11-30

申请号：US10157175

申请日：2002-05-29

申请人： Harry Hedler ,  Thorsten Meyer ,  Barbara Vasquez

发明人： Harry Hedler ,  Thorsten Meyer ,  Barbara Vasquez

IPC分类号： H05K500

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L23/49811 ,  H01L2924/0002 ,  H05K3/325 ,  H01L2924/00

摘要： An electronic structure includes an electronic component, which is configured to be in electric contact with a base and has a mounting side configured for mounting onto the base. The structure also includes a raised elastic support positioned on the component and multiple contacts positioned on the component, with at least one contact also being positioned on the support.

摘要翻译： 电子结构包括电子部件，其构造成与基座电接触，并且具有被配置为安装到基座上的安装侧。 该结构还包括定位在部件上的凸起弹性支撑件和位于部件上的多个触点，至少一个触点也位于支撑件上。

公开(公告)号：US5602491A

公开(公告)日：1997-02-11

申请号：US405317

申请日：1995-03-16

申请人： Barbara Vasquez ,  John W. Stafford ,  William M. Williams

发明人： Barbara Vasquez ,  John W. Stafford ,  William M. Williams

IPC分类号： G01R31/26 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66 ,  H01L23/373 ,  H05K3/42 ,  H05K3/46 ,  G01R31/02

CPC分类号： G01R31/2863 ,  G01R1/07314 ,  H01L23/3735 ,  H01L23/3737 ,  H05K3/4641 ,  H01L2924/0002 ,  H05K2201/015 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K3/429 ,  H05K3/4611

摘要： A board (10) for testing an integrated circuit disposed on a semiconductor wafer. The board contains a plurality of substantially parallel signal layers (14) and power planes (16) that are supported and electrically isolated by a dielectric material (12). One or more constraint layers (18,20) are disposed in the dielectric material, and the constraint layers have a coefficient of thermal expansion of about 1-6 ppm/.degree.C. In a preferred embodiment, the dielectric material is a fluoropolymer with-a ceramic or silica filler, and the constraint layers are an iron-nickel alloy of about 30-40 percent nickel by weight. The board has thermal expansion characteristics substantially similar to silicon to ensure good contact to a silicon wafer during burn-in testing.

摘要翻译： 一种用于测试设置在半导体晶片上的集成电路的板（10）。 电路板包含多个基本上平行的信号层（14）和电源层（16），其被电介质材料（12）支撑并电隔离。 一个或多个约束层（18,20）设置在电介质材料中，并且约束层的热膨胀系数为约1-6ppm /℃。在优选实施例中，电介质材料是含氟聚合物， 陶瓷或二氧化硅填料，约束层是约30-40重量％镍的铁镍合金。 该板具有基本上类似于硅的热膨胀特性，以确保在老化测试期间与硅晶片的良好接触。

公开(公告)号：US5175123A

公开(公告)日：1992-12-29

申请号：US612174

申请日：1990-11-13

申请人： Barbara Vasquez ,  Michael P. Masquelier

发明人： Barbara Vasquez ,  Michael P. Masquelier

IPC分类号： H01L21/32 ,  H01L21/762

CPC分类号： H01L21/76202 ,  H01L21/32 ,  Y10S148/117

摘要： A reduction in defects and lateral encroachment is obtained by utilizing a high pressure oxidation in conjunction with an oxidizable layer conformally deposited over an oxidation mask. The use of high pressure oxidation provides for the formation of LOCOS oxide without the formation of defects. Any native oxide present on the substrate surface is removed by using a ramped temperature deposition process to form oxidizable layer and/or a high temperature anneal is performed to remove the native oxide at the substrate surface. In this embodiment, any oxide which can act as a pipe for oxygen diffusion is removed. Therefore, nominal or no lateral encroachment is exhibited.

摘要翻译： 通过利用高压氧化与保形地沉积在氧化掩模上的可氧化层结合来获得缺陷和横向侵蚀的减少。 使用高压氧化提供形成LOCOS氧化物而不形成缺陷。 存在于衬底表面上的任何天然氧化物通过使用斜变温度沉积工艺以形成可氧化层而被去除，和/或进行高温退火以去除衬底表面处的自然氧化物。 在本实施例中，可以除去可充当氧扩散管的任何氧化物。 因此，表现为名义上或没有横向侵占。

公开(公告)号：US5156705A

公开(公告)日：1992-10-20

申请号：US580047

申请日：1990-09-10

申请人： Robert C. Kane ,  Barbara Vasquez

发明人： Robert C. Kane ,  Barbara Vasquez

IPC分类号： H01J9/02

CPC分类号： H01J9/025

摘要： A method for forming an electron emitter layer wherein the electron emitter layer comprises a plurality of elemental conductive materials that etch at dis-similar rates to provide a structure with an edge exhibiting a geometric discontinuity of small radius of curvature.

摘要翻译： 一种用于形成电子发射器层的方法，其中电子发射极层包括以不相似的速率蚀刻的多个元素导电材料，以提供具有表现出小曲率半径的几何不连续的边缘的结构。

公开(公告)号：US08324725B2

公开(公告)日：2012-12-04

申请号：US11160477

申请日：2005-06-24

申请人： Igor Y. Khandros ,  Charles A. Miller ,  Bruce J. Barbara ,  Barbara Vasquez

发明人： Igor Y. Khandros ,  Charles A. Miller ,  Bruce J. Barbara ,  Barbara Vasquez

IPC分类号： H01L23/485 ,  H01L21/00 ,  H01L25/16 ,  H01L25/065

CPC分类号： H01L24/48 ,  H01L23/13 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85186 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

摘要： Semiconductor dies are stacked offset from one another so that terminals located along two edges of each die are exposed. The two edges of the dies having terminals may be oriented in the same direction. Electrical connections may connect terminals on one die with terminals on another die, and the stack may be disposed on a wiring substrate to which the terminals of the dies may be electrically connected.

摘要翻译： 半导体管芯彼此堆叠地堆叠，使得沿着每个管芯的两个边缘定位的端子被暴露。 具有端子的模具的两个边缘可以沿相同的方向定向。 电连接可以将一个管芯上的端子连接到另一个管芯上的端子，并且堆叠可以设置在可以电连接管芯的端子的布线基板上。

公开(公告)号：US20060244109A1

公开(公告)日：2006-11-02

申请号：US11383341

申请日：2006-05-15

申请人： Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

发明人： Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

IPC分类号： H01L23/495

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166

摘要： A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region, application of a corrodible metalization layer to the dielectric, application of a protection device to the metalization layer, and removal of the protection device in a region around the connection region.

摘要翻译： 一种用于制造集成电路连接区域的方法包括将电介质施加到具有连接区域的集成电路，向电介质施加可腐蚀金属化层，向金属化层施加保护装置，以及将保护装置移除到 连接区域周围的区域。

公开(公告)号：US20060076690A1

公开(公告)日：2006-04-13

申请号：US11160477

申请日：2005-06-24

申请人： Igor Khandros ,  Charles Miller ,  Bruce Barbara ,  Barbara Vasquez

发明人： Igor Khandros ,  Charles Miller ,  Bruce Barbara ,  Barbara Vasquez

IPC分类号： H01L23/02 ,  H01L23/52

CPC分类号： H01L24/48 ,  H01L23/13 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85186 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

摘要： Semiconductor dies are stacked offset from one another so that terminals located along two edges of each die are exposed. The two edges of the dies having terminals may be oriented in the same direction. Electrical connections may connect terminals on one die with terminals on another die, and the stack may be disposed on a wiring substrate to which the terminals of the dies may be electrically connected.

摘要翻译： 半导体管芯彼此堆叠地堆叠，使得沿着每个管芯的两个边缘定位的端子被暴露。 具有端子的模具的两个边缘可以沿相同的方向定向。 电连接可以将一个管芯上的端子连接到另一个管芯上的端子，并且堆叠可以设置在可以电连接管芯的端子的布线基板上。

公开(公告)号：US20050110162A1

公开(公告)日：2005-05-26

申请号：US10960994

申请日：2004-10-12

申请人： Georg Meyer-Berg ,  Barbara Vasquez

发明人： Georg Meyer-Berg ,  Barbara Vasquez

IPC分类号： H01L21/00 ,  H01L21/48 ,  H01L21/60 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L23/50 ,  H01L23/52 ,  H01L25/065 ,  H05K1/03 ,  H05K3/40

CPC分类号： H01L21/4853 ,  H01L21/486 ,  H01L23/142 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3025 ,  H05K1/0306 ,  H05K3/4046 ,  H05K2201/0323 ,  H05K2201/10287 ,  H05K2203/0235 ,  H01L2924/00

摘要： An electronic component has a semiconductor chip and microscopically small flip-chip contacts belonging to a rewiring plate, on which macroscopically large elastic external contacts are arranged. The rewiring plate has a wiring support made of polycrystalline silicon, amorphous glass, or metal. Furthermore, the present invention relates to a method for the production of a suitable wiring support and of the electronic component.

摘要翻译： 电子部件具有属于重新布线板的半导体芯片和微小尺寸的倒装芯片触点，布置有宏观上大的弹性外部触点。 再布线板具有由多晶硅，非晶玻璃或金属制成的布线支撑。 此外，本发明涉及一种用于生产合适的布线支撑件和电子部件的方法。

公开(公告)号：US06845554B2

公开(公告)日：2005-01-25

申请号：US10298837

申请日：2002-11-18

申请人： Gerd Frankowsky ,  Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

发明人： Gerd Frankowsky ,  Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

IPC分类号： H01L21/00 ,  H01L21/60 ,  H01L21/78 ,  H05K3/30

CPC分类号： H01L24/96 ,  H01L21/67144 ,  H01L21/78 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49135 ,  Y10T29/49155 ,  Y10T29/53178

摘要： The invention creates a method for connection of circuit units (101a-10n) which are arranged on a wafer (100), in which the wafer (100) is fitted to a first film (102a), the wafer (100) is sawn such that the circuit units (101a-101n) which are arranged on the wafer (100) are separated, the functional circuit units (101d) are picked up by means of a handling device (101) and are placed down on a second film (102b) by means of the handling device (103), so as to produce a separation distance which can be predetermined between connection contacts of the circuit units (101d).

摘要翻译： 本发明创造了一种用于连接电路单元（101a-10n）的方法，它们布置在晶片（100）上，其中晶片（100）装配到第一薄膜（102a）上，晶片（100）被锯切 布置在晶片（100）上的电路单元（101a-101n）被分离，功能电路单元（101d）通过处理装置（101）拾取并放置在第二薄膜（102b）上 ），以便产生可以在电路单元（101d）的连接触点之间预定的间隔距离。