公开(公告)号：US20130207240A1

公开(公告)日：2013-08-15

申请号：US13829802

申请日：2013-03-14

Applicant: XINTEC INC.

Inventor： Hung-Jen LEE ,  Shu-Ming CHANG ,  Chen-Han CHIANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

Abstract: An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

Abstract translation: 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定在其上的多个预定划线的第一基板，其中，所述预定划线限定多个器件区域; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环和位于芯片支撑环的周边的切割支撑结构，并且间隔层具有 将切割支撑结构与芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一个实施例提供一种芯片封装结构。

公开(公告)号：US20240109769A1

公开(公告)日：2024-04-04

申请号：US18538503

申请日：2023-12-13

Applicant: Xintec Inc.

Inventor： Wei-Luen SUEN ,  Jiun-Yen LAI ,  Hsing-Lung SHEN ,  Tsang-Yu LIU

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0067 ,  B81C1/00317 ,  B81B2203/0353 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0194

Abstract: A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.

公开(公告)号：US20220285423A1

公开(公告)日：2022-09-08

申请号：US17683917

申请日：2022-03-01

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Shu-Ming CHANG ,  Chaung-Lin LAI

IPC: H01L27/146 ,  H01L23/544

Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having upper and lower surfaces, and having a chip region and a scribe-line region surrounding the chip region. The substrate has a dielectric layer on its upper surface. A masking layer is formed over the substrate to cover the dielectric layer. The masking layer has a first opening exposing the dielectric layer and extending in the extending direction of the scribe-line region to surround the chip region. An etching process is performed on the dielectric layer directly below the first opening, to form a second opening that is in the dielectric layer directly below the first opening. The masking layer is removed to expose the dielectric layer having the second opening. A dicing process is performed on the substrate through the second opening.

公开(公告)号：US20210032096A1

公开(公告)日：2021-02-04

申请号：US16941465

申请日：2020-07-28

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Chaung-Lin LAI ,  Shu-Ming CHANG

IPC: B81B7/00 ,  B81C1/00

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

公开(公告)号：US20200044099A1

公开(公告)日：2020-02-06

申请号：US16512244

申请日：2019-07-15

Applicant: XINTEC INC.

Inventor： Shu-Ming CHANG ,  Tsang-Yu LIU

IPC: H01L31/0216 ,  H01L33/62 ,  H01L31/02 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/14

Abstract: A chip package is provided. the chip package includes a substrate having an upper surface, a lower surface, and a sidewall surface that is at an edge of the substrate. The substrate includes a sensing device adjacent to the upper surface of the substrate to sense a light source. The chip package also includes a first color filter layer disposed on the upper surface of the substrate to shield the light source. The first color filter layer includes an opening, so that the first color filter layer surrounds the sensing device via the opening. In addition, the chip package includes a redistribution layer disposed on the lower surface of the substrate. A method of forming the chip package is also provided.

公开(公告)号：US20170179330A1

公开(公告)日：2017-06-22

申请号：US15451202

申请日：2017-03-06

Applicant: XINTEC INC.

Inventor： Wei-Luen SUEN ,  Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L31/18 ,  H01L31/0203 ,  H01L31/0236 ,  H01L31/02

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L23/3114 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/11

Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.

公开(公告)号：US20170117242A1

公开(公告)日：2017-04-27

申请号：US15297490

申请日：2016-10-19

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Po-Han LEE ,  Chi-Chang LIAO

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/06181 ,  H01L2224/08265 ,  H01L2224/1403 ,  H01L2224/14155 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/146

Abstract: A chip package is provided. The chip package includes a substrate. The substrate includes a sensing region or device region. The chip package also includes a first conducting structure disposed on the substrate. The first conducting structure is electrically connected to the sensing region or device region. The chip package further includes a passive element vertically stacked on the substrate. The passive element and the first conducting structure are positioned side by side.

公开(公告)号：US20170116458A1

公开(公告)日：2017-04-27

申请号：US15297546

申请日：2016-10-19

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Ying-Nan WEN ,  Chi-Chang LIAO ,  Yu-Lung HUANG

IPC: G06K9/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/08 ,  H01L21/78 ,  H01L23/31 ,  H01L23/04 ,  H01L21/683 ,  H01L21/56

CPC classification number: G06K9/00013 ,  G06K19/0716 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76895 ,  H01L21/78 ,  H01L23/04 ,  H01L23/08 ,  H01L23/15 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/0579 ,  H01L2224/058 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A method for forming a sensing device includes providing a first substrate. The first substrate has a first surface and a second surface opposite thereto. A sensing region is adjacent to the first surface. A temporary cover plate is provided on the second surface to cover the sensing region. The method also includes forming a redistribution layer on the second surface and electrically connected to the sensing region. The method further includes removing the temporary cover plate after the formation of the redistribution layer. The first substrate is bonded to a second substrate and a cover plate after the removal of the temporary cover plate so that the first substrate is positioned between the second substrate and the cover plate. In addition, the method includes filling an encapsulating layer between the second substrate and the cover plate to surround the first substrate.

公开(公告)号：US20160351607A1

公开(公告)日：2016-12-01

申请号：US15166261

申请日：2016-05-27

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Chi-Chang LIAO

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/14601 ,  H01L27/14687 ,  H04N5/2253

Abstract: An image sensing device includes a printed circuit board, a chip package, and an adhesive layer. The printed circuit board has a concave portion. The chip package has a sensing surface and a bonding surface that is opposite to the sensing surface. The adhesive layer is disposed between the bonding surface of the chip package and the concave portion of the printed circuit board. The adhesive layer has an aggregation force. The chip package is bent through a surface of the concave portion and the aggregation force, such that the sensing surface of the chip package is an arc surface.

Abstract translation: 图像感测装置包括印刷电路板，芯片封装和粘合剂层。 印刷电路板具有凹部。 芯片封装具有感测表面和与感测表面相对的接合表面。 粘合剂层设置在芯片封装的接合表面和印刷电路板的凹部之间。 粘合剂层具有聚集力。 芯片封装通过凹部的表面和聚集力弯曲，使得芯片封装的感测表面是弧形表面。

公开(公告)号：US20160284751A1

公开(公告)日：2016-09-29

申请号：US15062020

申请日：2016-03-04

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Po-Han LEE ,  Jiun-Yen LAI

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  A61B5/1172 ,  B81B7/0067 ,  B81B7/007 ,  B81B2207/096 ,  G06K9/0004 ,  H01L21/76898 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0362 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/0579 ,  H01L2224/058 ,  H01L2224/11 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/0665

Abstract: This present invention provides a chip scale sensing chip package, comprising a sensing chip having a first top surface and a first bottom surface opposite to the first top surface, which comprises a sensing device near the first top surface, a plurality of conductive pads near the first top surface and adjacent to the sensing device; a plurality of through holes on the first top surface and each of the through holes exposing one of the conductive pads corresponding to with each other; a plurality of conductive structure formed on the first bottom surface; and a re-distribution layer (RDL) formed on the first bottom surface and the first through holes to respectively connect to each of the conductive pads and each of the conductive structures; a spacing layer, surrounding the sensing chip, formed on the sensing chip. The spacing layer has a second top surface, a second bottom surface and an opening through the second top surface and the second bottom surface, wherein the opening corresponds to the sensing device and the inner wall of the opening remains a desired distance d (d>0) with the sensing device; and a first adhesive layer sandwiched between the second bottom surface of the spacing layer and the first top surface of the sensing chip.

Abstract translation: 本发明提供了一种芯片尺度感测芯片封装，其包括具有第一顶表面和与第一顶表面相对的第一底表面的感测芯片，其包括靠近第一顶表面的感测装置，靠近第一顶表面的多个导电垫 第一顶表面并邻近感测装置; 所述第一顶表面上的多个通孔和每个所述通孔暴露彼此对应的所述导电焊盘之一; 形成在所述第一底面上的多个导电结构; 以及形成在所述第一底表面上的再分布层（RDL）和所述第一通孔，以分别连接到每个所述导电焊盘和每个所述导电结构; 围绕感测芯片的间隔层，形成在感测芯片上。 间隔层具有第二顶表面，第二底表面和穿过第二顶表面和第二底表面的开口，其中开口对应于感测装置，并且开口的内壁保持期望的距离d（d> 0）与感测装置; 以及夹在间隔层的第二底表面和感测芯片的第一顶表面之间的第一粘合剂层。