公开(公告)号：US07049694B2

公开(公告)日：2006-05-23

申请号：US11270300

申请日：2005-11-09

Applicant: Yaping Zhou ,  Chu-Chung Lee

Inventor： Yaping Zhou ,  Chu-Chung Lee

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L24/85 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45166 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45684 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00

Abstract: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.

公开(公告)号：US20060065966A1

公开(公告)日：2006-03-30

申请号：US11270300

申请日：2005-11-09

Applicant: Yaping Zhou ,  Chu-Chung Lee

Inventor： Yaping Zhou ,  Chu-Chung Lee

IPC: H01L23/52

CPC classification number: H01L24/85 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45166 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45684 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00

Abstract: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.

公开(公告)号：US06992377B2

公开(公告)日：2006-01-31

申请号：US10787288

申请日：2004-02-26

Applicant: Yaping Zhou ,  Chu-Chung Lee

Inventor： Yaping Zhou ,  Chu-Chung Lee

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L24/85 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45166 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45684 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00

Abstract: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.

公开(公告)号：US20160072640A1

公开(公告)日：2016-03-10

申请号：US14388408

申请日：2012-03-29

Applicant: Juan Yang ,  Yaping Zhou ,  Ke Lin

Inventor： Juan Yang ,  Yaping Zhou ,  Ke Lin

IPC: H04L12/437 ,  H04L29/12 ,  H04L12/801 ,  H04L12/755

CPC classification number: H04L12/437 ,  H04L45/021 ,  H04L47/12 ,  H04L61/6022

Abstract: Embodiments of the present invention provide a method and system for reducing congestion on a communication network. The communication network includes a network node having a first port and a second port. The network node is associated with forwarding data including first port forwarding data identifying at least one node accessible via the first port, and second port forwarding data identifying at least one node accessible via the second port. A failure associated with one of the first port and the second port is determined. The forwarding data corresponding to the other of the first port and the second port not associated with the failure, is updated with the one of the first port forwarding data and second port forwarding data corresponding to the one of the first port and the second port associated with the failure.

Abstract translation: 本发明的实施例提供一种减少通信网络拥塞的方法和系统。 通信网络包括具有第一端口和第二端口的网络节点。 网络节点与转发数据相关联，转发数据包括识别经由第一端口可访问的至少一个节点的第一端口转发数据，以及识别经由第二端口可访问的至少一个节点的第二端口转发数据。 确定与第一端口和第二端口之一相关联的故障。 与第一端口和第二端口中的另一端对应的转发数据被更新为与第一端口和第二端口相关联的第一端口转发数据和第二端口转发数据之一相对应 失败了。

公开(公告)号：US08791372B2

公开(公告)日：2014-07-29

申请号：US13426892

申请日：2012-03-22

Applicant: Paul M. Harvey ,  Douglas O. Powell ,  Wolfgang Sauter ,  Yaping Zhou

Inventor： Paul M. Harvey ,  Douglas O. Powell ,  Wolfgang Sauter ,  Yaping Zhou

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0233 ,  H05K1/112 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/086 ,  H05K2201/09536 ,  H05K2201/096

Abstract: A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.

Abstract translation: 具有电镀通孔（PTH）的器件和/或设备，其被涂覆以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。 迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。

公开(公告)号：US08742565B2

公开(公告)日：2014-06-03

申请号：US13687218

申请日：2012-11-28

Applicant: Roger D. Weekly ,  Yaping Zhou

Inventor： Roger D. Weekly ,  Yaping Zhou

IPC: H01L23/48

CPC classification number: H01L23/49816 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.

Abstract translation: 一种用于分配电源和接地引脚以及用于球栅阵列半导体封装的单端或差分信号对的改进的系统和方法。 在某些实施例中，系统使用六边形图案，其中网格可以由多个嵌套的六边形图案表示。

公开(公告)号：US08222739B2

公开(公告)日：2012-07-17

申请号：US12642806

申请日：2009-12-19

Applicant: Paul M. Harvey ,  Colm B. O'Reilly ,  Samuel W. Yang ,  Yaping Zhou

Inventor： Paul M. Harvey ,  Colm B. O'Reilly ,  Samuel W. Yang ,  Yaping Zhou

IPC: H01L23/48 ,  H01L21/00 ,  B23K31/02

CPC classification number: H01L23/645 ,  H01L21/563 ,  H01L23/295 ,  H01L23/49816 ,  H01L23/552 ,  H01L2224/13022 ,  H01L2224/73203 ,  H01L2924/01077 ,  H01L2924/3011 ,  H05K1/0233 ,  H05K2201/10977 ,  Y10T29/49147

Abstract: A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.

Abstract translation: 改进核心封装连接的系统可以包括球栅阵列焊盘和球栅阵列。 该系统还可以包括导电连接到相应的球栅阵列焊盘的球栅阵列的连接构件。 该系统还可以包括邻近至少一些连接构件和相应的球栅阵列垫定位的磁性底部填充，以增加各自的连接构件的电感。

公开(公告)号：US08193800B2

公开(公告)日：2012-06-05

申请号：US12020882

申请日：2008-01-28

Applicant: Yaping Zhou

Inventor： Yaping Zhou

IPC: G05F1/00 ,  H02J1/02

CPC classification number: H02J1/02 ,  H02M1/14

Abstract: A method and system for reducing the noise level of a power supply system with the implementation of a voltage controlled decoupling capacitor in an electrical circuit. Voltage variations of the power supply caused by switching currents are detected by a voltage sensor control circuit. The voltage sensor circuit compares a stable reference voltage with the varying voltage level of the power supply in order to generate a sensor control voltage. When applied to the decoupling capacitor, the control voltage adjusts the capacitance of the voltage controlled capacitor. The adjusted capacitance allows the voltage controlled decoupling capacitor to compensate for the effects of the voltage variations by supplying an increased quantity of charge to various circuit components. Thus, the voltage controlled capacitor is able to efficiently reduce noise within the power supply system.

Abstract translation: 一种用于在电路中实施电压控制的去耦电容器来降低电源系统的噪声电平的方法和系统。 由开关电流引起的电源的电压变化由电压传感器控制电路检测。 电压传感器电路将稳定的参考电压与电源的变化的电压电平进行比较，以便产生传感器控制电压。 当施加到去耦电容器时，控制电压调节压控电容器的电容。 经调整的电容允许电压控制去耦电容器通过向各种电路部件提供增加的电荷来补偿电压变化的影响。 因此，压控电容器能够有效地降低供电系统内的噪声。

公开(公告)号：US20100017158A1

公开(公告)日：2010-01-21

申请号：US12176811

申请日：2008-07-21

Applicant: Rohan Mandrekar ,  Paul Marlan Harvey ,  Yaping Zhou ,  Kazushige Kawasaki

Inventor： Rohan Mandrekar ,  Paul Marlan Harvey ,  Yaping Zhou ,  Kazushige Kawasaki

IPC: G01R29/26

CPC classification number: G01R31/318385 ,  G01R31/318307

Abstract: A methodology to determine a bit pattern that may excite a worse case or near worse case simultaneous switching noise on a memory or input/output (IO) interface of a digital system is provided. This methodology involves determining an impedance profile of the IO interface of the digital system. The amplitude response of signal X(f) may be matched in the impedance profile of the IO interface. The phase response of the signal X(f) is also set. The signal X(f) having a matched amplitude response may be converted from a frequency domain signal to a time domain signal to produce a signal X(t). Signal X(t) the time domain signal X(t) may be digitized to represent a bit stream B(t). This bit stream may be used as a switching pattern to determine simultaneous switching noise of the IO interface of the digital system

Abstract translation: 提供了一种确定可能激发更糟糕情况或接近较差情况的位模式的方法，用于在数字系统的存储器或输入/输出（IO）接口上同时切换噪声。 该方法涉及确定数字系统的IO接口的阻抗曲线。 信号X（f）的振幅响应可以在IO接口的阻抗曲线上匹配。 信号X（f）的相位响应也被设定。 具有匹配振幅响应的信号X（f）可以从频域信号转换为时域信号以产生信号X（t）。 时域信号X（t）的信号X（t）可以被数字化以表示比特流B（t）。 该比特流可以用作切换模式以确定数字系统的IO接口的同时切换噪声

公开(公告)号：US06998952B2

公开(公告)日：2006-02-14

申请号：US10729531

申请日：2003-12-05

Applicant: Yaping Zhou ,  Susan H. Downey ,  Sheila F. Chopin ,  Tu-Anh Tran ,  Alan H. Woosley ,  Peter R. Harper ,  Perry H. Pelley, III

Inventor： Yaping Zhou ,  Susan H. Downey ,  Sheila F. Chopin ,  Tu-Anh Tran ,  Alan H. Woosley ,  Peter R. Harper ,  Perry H. Pelley, III

IPC: H01F27/06 ,  H01F5/00

CPC classification number: H01F17/0033 ,  H01F41/046 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3025 ,  Y10T29/4902 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An inductive device (105) is formed above a substrate (225) having a conductive coil formed around a core (109). The coil comprises segments formed from a first plurality of bond wires (113) and a second plurality of bond wires (111). The first plurality of bond wires (113) extends between the core (109) and the substrate (225). Each of the first plurality of bond wires is coupled to two of a plurality of wire bond pads (117, 116). The second plurality of bond wires (111) extends over the core (109) and is coupled between two of the plurality of wire bond pads (117, 119). A shield (141) includes a portion that is positioned between the core (109) and the substrate (225).

Abstract translation: 在具有围绕芯（109）形成的导电线圈的衬底（225）上方形成感应器件（105）。 线圈包括由第一多个接合线（113）和第二多个接合线（111）形成的线段。 第一多个接合线（113）在芯（109）和衬底（225）之间延伸。 第一多个接合线中的每一个耦合到多个引线接合焊盘（117,116）中的两个。 所述第二多个接合线（111）在所述芯（109）上方延伸并耦合在所述多个引线接合焊盘（117,119）中的两个之间。 屏蔽（141）包括位于芯（109）和衬底（225）之间的部分。