公开(公告)号：US20100294342A1

公开(公告)日：2010-11-25

申请号：US12783859

申请日：2010-05-20

申请人： Hiroyuki Nakanishi ,  Kohji Miyata ,  Yoshihide Iwazaki ,  Seiji Ishihara ,  Masato Yokobayashi ,  Etsuko Ishizuka ,  Kiyoharu Shimano ,  Katsunobu Mori

发明人： Hiroyuki Nakanishi ,  Kohji Miyata ,  Yoshihide Iwazaki ,  Seiji Ishihara ,  Masato Yokobayashi ,  Etsuko Ishizuka ,  Kiyoharu Shimano ,  Katsunobu Mori

IPC分类号： H01L31/048 ,  H01L31/18

CPC分类号： H01L31/0508 ,  H01L31/0201 ,  H01L31/048 ,  H01L31/0504 ,  H01L31/0512 ,  Y02E10/50

摘要： A solar cell module 1 includes a plurality of solar cells 30. Each of the plurality of solar cells 30 is disposed on a corresponding one of a plurality of pad sections in such a manner that the each of the plurality of solar cells 30 is electrically connected to the corresponding one of the plurality of pad sections. The each of the plurality of solar cells 30 is electrically connected to a corresponding inner lead section 120. A cathode section 114 and an anode section 116 feed an electric current generated by the plurality of solar cells 30. A metal lead frame is provided such that the plurality of pad sections, the inner lead sections 120, the cathode section 114 and the anode section 116 are provided therein as a part of the lead frame itself. This configuration enables the solar cell module 1 to endure against bending stress and to be curved. As a result, it is possible to provide a solar cell module which can be disposed along a curved surface of an electronics device.

摘要翻译： 太阳能电池模块1包括多个太阳能电池30.多个太阳能电池30中的每一个以多个太阳能电池30中的每一个电连接的方式设置在多个焊盘部分中的相应的一个上 到多个垫部分中的对应的一个。 多个太阳能电池30中的每一个电连接到相应的内部引线部分120.阴极部分114和阳极部分116馈送由多个太阳能电池30产生的电流。金属引线框架设置成使得 多个焊盘部分，内部引线部分120，阴极部分114和阳极部分116作为引线框架本身的一部分设置在其中。 这种构造使得太阳能电池模块1能够耐受弯曲应力并弯曲。 结果，可以提供一种可以沿着电子设备的曲面布置的太阳能电池模块。

公开(公告)号：US06921980B2

公开(公告)日：2005-07-26

申请号：US10059113

申请日：2002-01-31

申请人： Hiroyuki Nakanishi ,  Toshiya Ishio ,  Katsunobu Mori

发明人： Hiroyuki Nakanishi ,  Toshiya Ishio ,  Katsunobu Mori

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/3114 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/05166 ,  H01L2924/00012

摘要： An integrated semiconductor circuit includes a semiconductor chip on which surface a plurality of connection electrodes are formed, a lower insulating layer covering the surface of the semiconductor chip such that the connection electrodes are exposed, a plurality of wiring portions formed on the lower insulating layer, each of the wiring portions being connected to the connection electrode at one end and provided with a component connection portion at the other end, an upper insulating layer covering the wiring portions such that the component connection portions are exposed, and an electronic component connected between different component connection portions.

摘要翻译： 集成半导体电路包括其上形成有多个连接电极的表面的半导体芯片，覆盖半导体芯片的表面的下绝缘层，使得连接电极露出，形成在下绝缘层上的多个布线部分， 每个布线部分在一端连接到连接电极，并且在另一端处设置有部件连接部分，覆盖布线部分的上绝缘层使得部件连接部分暴露，以及连接在不同的部件之间的电子部件 部件连接部分。

公开(公告)号：US6104084A

公开(公告)日：2000-08-15

申请号：US61035

申请日：1998-04-16

申请人： Toshiya Ishio ,  Hiroyuki Nakanishi ,  Tomoyo Maruyama ,  Katsunobu Mori ,  Katsuyuki Tarui

发明人： Toshiya Ishio ,  Hiroyuki Nakanishi ,  Tomoyo Maruyama ,  Katsunobu Mori ,  Katsuyuki Tarui

IPC分类号： H01L25/18 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/49 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/32 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/351

摘要： An insulation material and a wire pattern are provided on at least one of the surfaces of a die pad. Wires of the wire pattern are patterned in such a manner that at least one inner lead included in at least one of two lead groups is electrically connected to an electrode pad provided on the element forming surface of the semiconductor chip near the side edge other than the side edge opposing the lead group including the above particular inner lead, while at least one inner lead included in the other lead group is electrically connected to an electrode pad provided on the element forming surface of the semiconductor chip near the side edge other than the side edge opposing the other lead group. Accordingly, a multichip-1-package semiconductor device using any kind of semiconductor chip can be realized. Also, the costs of the semiconductor device are saved and the semiconductor device can be developed in a shorter period by omitting the design modification of the semiconductor chip.

摘要翻译： 在芯片焊盘的至少一个表面上设置绝缘材料和导线图案。 线图案的线图案化为使得包括在两个引线组中的至少一个中的至少一个内引线电连接到设置在半导体芯片的元件形成表面附近的电极焊盘，该电极焊盘靠近除了 与包括上述特定内引线的引线组相对的侧边缘，而另一引线组中包括的至少一个内引线电连接到设置在半导体芯片的元件形成表面上的电极焊盘，靠近侧边 边缘反对另一个领导组。 因此，可以实现使用任何种类的半导体芯片的多芯片1封装半导体器件。 此外，通过省略半导体芯片的设计修改，节省了半导体器件的成本，并且可以在更短的时间内开发半导体器件。

公开(公告)号：US06784528B2

公开(公告)日：2004-08-31

申请号：US10269074

申请日：2002-10-11

申请人： Hiroyuki Nakanishi ,  Toshiya Ishio ,  Katsunobu Mori

发明人： Hiroyuki Nakanishi ,  Toshiya Ishio ,  Katsunobu Mori

IPC分类号： H01L2302

CPC分类号： H01L24/25 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L29/0657 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00014

摘要： In order to simplify a providing method of a wiring that electrically connects a semiconductor integrated circuit to a substrate, the semiconductor integrated circuit that is covered with an insulating layer except for an electrode area having an electrode pad is fixed on a formation side of the substrate having a terminal connected to the semiconductor integrated circuit so that the electrode pad is exposed. Next, a metallic thin film is provided on a wiring area on which a wiring for electrically connecting the electrode pad to the terminal is provided. Further, the wiring is provided on the metallic film of the wiring area in accordance with plating.

摘要翻译： 为了简化将半导体集成电路电连接到基板的布线的提供方法，除了具有电极焊盘的电极区域之外被绝缘层覆盖的半导体集成电路固定在基板的形成侧 具有连接到半导体集成电路的端子，使得电极焊盘露出。 接下来，在布线区域上设置金属薄膜，在该区域上设置用于将电极焊盘与端子电连接的布线。 此外，根据电镀将布线设置在布线区域的金属膜上。

公开(公告)号：US6118184A

公开(公告)日：2000-09-12

申请号：US108806

申请日：1998-07-01

申请人： Toshiya Ishio ,  Hiroyuki Nakanishi ,  Katsunobu Mori ,  Katsuyuki Tarui

发明人： Toshiya Ishio ,  Hiroyuki Nakanishi ,  Katsunobu Mori ,  Katsuyuki Tarui

IPC分类号： H01L25/18 ,  H01L21/56 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07 ,  H01L23/28 ,  H01L21/60 ,  H01L23/48

CPC分类号： H01L23/49575 ,  H01L21/565 ,  H01L23/49503 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01004 ,  H01L2924/01014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181

摘要： A method of manufacturing a semiconductor device including two semiconductor chips having mutually different element forming face areas on respective surfaces of a die pad of a lead frame prepared by sealing the semiconductor chips with resin by setting the lead frame in a resin sealing use mold having an injection gate for injecting therethrough a sealing resin, includes the steps of: (a) mounting the semiconductor chips on respective surfaces of the die pad in such a manner that when setting the lead frame in the resin sealing use mold, a distance between a side face of the semiconductor chip having a larger element forming face area on the injection gate side and a side face of the semiconductor chip having a smaller element forming face area on the injection gate side becomes shorter than a distance when these semiconductor chips are mounted at a center on respective surfaces of the die pad; (b) setting the lead frame in the resin sealing use mold so that the above side faces of the semiconductor chips are positioned on the injection gate side; and (c) injecting the sealing resin from the injection gate.

摘要翻译： 一种制造半导体器件的方法，该半导体器件包括两个半导体芯片，该两个半导体芯片在引线框架的裸片焊盘的各个表面上具有相互不同的元件形成面区域，该引线框架通过将引线框架设置在具有 用于通过其注入密封树脂的注入门包括以下步骤：（a）将半导体芯片安装在管芯焊盘的各个表面上，使得当将引线框架设置在树脂密封用模具中时，侧面之间的距离 在注入栅侧具有较大元件形成面区域的半导体芯片的表面和在注入栅极侧具有较小元件形成面区域的半导体芯片的侧面变得比这些半导体芯片安装在 中心在芯片的各个表面上; （b）将引线框架设置在树脂密封用模具中，使得半导体芯片的上述侧面位于注入口侧; 和（c）从注入口注入密封树脂。

公开(公告)号：US20060163728A1

公开(公告)日：2006-07-27

申请号：US11334485

申请日：2006-01-19

申请人： Hiroyuki Nakanishi ,  Katsunobu Mori

发明人： Hiroyuki Nakanishi ,  Katsunobu Mori

IPC分类号： H01L23/48

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2224/96 ,  H01L2224/82

摘要： A semiconductor device includes: a semiconductor chip having a plurality of electrode pads formed on a principal surface thereof; a sealing resin, which covers both (i) side surfaces of the semiconductor chip and (ii) a surface of the semiconductor chip opposite to the principal surface; and external connection pads, which are provided on both (I) the principal surface and (II) a surface of the sealing resin flush with the principal surface, and which are electrically connected to the electrode pads. Thus, a semiconductor device is provided which makes it possible to place external connection pads at wider intervals, and which makes it possible to widen wires and to place the wires at wider intervals.

摘要翻译： 半导体器件包括：具有形成在其主表面上的多个电极焊盘的半导体芯片; 密封树脂，其覆盖半导体芯片的（i）侧表面和（ii）半导体芯片的与主表面相对的表面; 以及外部连接焊盘，其设置在主表面上的（I）主表面和（II）密封树脂的与主表面齐平的表面，并且与电极焊盘电连接。 因此，提供了一种半导体器件，其使得可以以更宽的间隔放置外部连接焊盘，并且这使得可以加宽电线并且以更宽的间隔放置电线。

公开(公告)号：US5506444A

公开(公告)日：1996-04-09

申请号：US212786

申请日：1994-03-15

申请人： Yasunori Chikawa ,  Yoshiaki Honda ,  Katsunobu Mori ,  Naoyuki Tajima ,  Takaaki Tsuda ,  Takamichi Maeda ,  Mitsuaki Osono

发明人： Yasunori Chikawa ,  Yoshiaki Honda ,  Katsunobu Mori ,  Naoyuki Tajima ,  Takaaki Tsuda ,  Takamichi Maeda ,  Mitsuaki Osono

IPC分类号： H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/495 ,  H01L23/28

CPC分类号： H01L21/56 ,  H01L23/293 ,  H01L23/3121 ,  H01L2924/0002

摘要： In a semiconductor device of a tape carrier package type, the gap width between inner leads connected with a first edge side of a semiconductor chip set within a device mounting hole provided in the tape carrier is larger than the gap width between leads connected with a second edge side opposite to the first edge side of the semiconductor chip, and the gap length of device mounting hole between the first edge of the semiconductor chip and the first edge of the device mounting hole corresponding to the first edge of the semiconductor chip is smaller than the gap length between the second edge of the semiconductor chip and the second edge of the device mounting hole corresponding to the second edge of the semiconductor chip. Such structure enables an encapsulation resin to fill uniformly the device mounting hole, and the encapsulation resin after encapsulation has a shape of a designed dimension.

摘要翻译： 在载带封装型的半导体器件中，与设置在带载体中的器件安装孔内的半导体芯片的与第一边缘侧连接的内部引线之间的间隙宽度大于与第二引线连接的引线之间的间隙宽度 边缘侧与半导体芯片的第一边缘侧相对，并且半导体芯片的第一边缘与对应于半导体芯片的第一边缘的器件安装孔的第一边缘之间的器件安装孔的间隙长度小于 半导体芯片的第二边缘与器件安装孔的与半导体芯片的第二边缘对应的第二边缘之间的间隙长度。 这样的结构能够使封装树脂均匀地填充装置安装孔，并且封装后的封装树脂具有设计尺寸的形状。

公开(公告)号：US5614760A

公开(公告)日：1997-03-25

申请号：US386051

申请日：1995-02-07

申请人： Mitsuaki Osono ,  Naoyuki Tajima ,  Katsunobu Mori

发明人： Mitsuaki Osono ,  Naoyuki Tajima ,  Katsunobu Mori

IPC分类号： H01L21/60 ,  H01L21/56 ,  H01L23/28 ,  H01L23/495 ,  H01L23/34 ,  H01L23/48

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01033 ,  H01L2924/01082

摘要： In a TCP (tape carrier package) semiconductor device having opposing, inner lead arrays bonded to a semiconductor device, a projection or projections are provided on each of the inner leads disposed at intervals of a greater distance on one side of the semiconductor, within a range for allowing the resin to flow out.

摘要翻译： 在具有接合到半导体器件的相对的内引线阵列的TCP（带载封装）半导体器件中，在半导体的一侧上以更大距离的间隔设置的每个内引线上设置有突起或突起， 允许树脂流出的范围。

公开(公告)号：US5604379A

公开(公告)日：1997-02-18

申请号：US452691

申请日：1995-05-30

申请人： Katsunobu Mori

发明人： Katsunobu Mori

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/822 ,  H01L23/12 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01L27/04 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L24/11 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5328 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02319 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041

摘要： A semiconductor device comprising a semiconductor chip, a plurality of electrode pads formed on the semiconductor chip, a metal wiring having a desired pattern and connected to the electrode pads, an anisotropic conductive film containing fine conductive particles and laminated on the semiconductor chip including the metal wiring, and an external electrode, in which the anisotropic conductive film has a concave portion at a desired portion on the metal wiring and the metal wiring is connected to the external electrode through the intermediary of the fine conductive particles present in the anisotropic conductive film by stuffing and sticking the external electrode in the concave portion.

摘要翻译： 一种半导体器件，包括半导体芯片，形成在半导体芯片上的多个电极焊盘，具有期望图案并连接到电极焊盘的金属布线，包含导电粒子的各向异性导电膜，层压在包括金属的半导体芯片上 布线和外部电极，其中各向异性导电膜在金属布线的期望部分具有凹部，并且金属布线通过介于各向异性导电膜中存在的微细导电颗粒的介质与外部电极连接， 将外部电极填充并粘贴在凹部中。

公开(公告)号：US5336650A

公开(公告)日：1994-08-09

申请号：US112315

申请日：1993-08-27

申请人： Yasunori Chikawa ,  Yoshiaki Honda ,  Katsunobu Mori ,  Naoyuki Tajima ,  Takaaki Tsuda ,  Takamichi Maeda

发明人： Yasunori Chikawa ,  Yoshiaki Honda ,  Katsunobu Mori ,  Naoyuki Tajima ,  Takaaki Tsuda ,  Takamichi Maeda

IPC分类号： H01L21/60 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31

CPC分类号： H01L21/56 ,  H01L23/293 ,  H01L23/3121 ,  H01L2924/0002 ,  Y10T29/49121

摘要： A tape carrier semiconductor device has a resin sealed area not so larger than the size of the semiconductor chip, e.g. substantially not exceeding 2 mm to the outside. A device hole is not larger than an area formed by extending the outer periphery of the semiconductor chip to the outside by 0.3 mm and an epoxy resin of 500-1200 ps in viscosity is used for sealing the chip.

摘要翻译： 带载半导体器件具有树脂密封区域不大于半导体芯片的尺寸，例如， 基本上不超过2mm。 器件孔不大于通过将半导体芯片的外周向外延伸0.3mm而形成的区域，并且使用粘度为500-1200ps的环氧树脂来密封芯片。