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公开(公告)号：US09469522B2
公开(公告)日：2016-10-18
申请号：US14201453
申请日：2014-03-07
Applicant: Robert Bosch GmbH
Inventor： Andrew Graham , Gary Yama , Gary O'Brien
CPC classification number: B81B3/0021 , B81B2201/0271 , B81B2203/04 , B81B2203/053 , B81C1/00095 , B81C1/00166 , B81C2201/0132 , B81C2201/014 , B81C2201/0177 , B81C2203/0136
Abstract: In one embodiment, a method of forming an out-of-plane electrode includes forming an oxide layer above an upper surface of a device layer, etching an etch stop perimeter defining trench extending through the oxide layer, forming a first cap layer portion on an upper surface of the oxide layer and within the etch stop perimeter defining trench, etching a first electrode perimeter defining trench extending through the first cap layer portion and stopping at the oxide layer, depositing a first material portion within the first electrode perimeter defining trench, depositing a second cap layer portion above the deposited first material portion, and vapor releasing a portion of the oxide layer with the etch stop portion providing a lateral etch stop.
Abstract translation: 在一个实施例中，形成平面外电极的方法包括在器件层的上表面上形成氧化物层，蚀刻限定延伸穿过氧化物层的沟槽的蚀刻停止周界，在第一帽层部分上形成 氧化物层的上表面，并且在蚀刻停止周界内限定沟槽，蚀刻延伸穿过第一盖层部分并停止在氧化物层处的第一电极周界，限定沟槽，在第一电极周界限定沟槽内沉积第一材料部分，沉积 在沉积的第一材料部分上方的第二盖层部分，以及用蚀刻停止部分提供横向蚀刻停止物的一部分氧化物层的蒸气。
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公开(公告)号：US09340412B2
公开(公告)日：2016-05-17
申请号：US14444921
申请日：2014-07-28
Applicant: ams International AG
Inventor： Willem Besling , Remco Henricus Wilhelmus Pijnenburg , Casper van der Avoort , Marten Oldsen , Martijn Goossens
CPC classification number: B81C1/00158 , B81C1/00246 , B81C2201/014 , G01L9/0042 , G01L9/0072 , G01L9/0073 , G01L9/12 , H01L29/84
Abstract: Embodiments of a method for forming a suspended membrane include depositing a first electrically conductive material above a sacrificial layer and within a boundary trench. The first electrically conductive material forms a corner transition portion above the boundary trench. The method further includes removing a portion of the first electrically conductive material that removes at least a portion of uneven topography of the first electrically conductive material. The method further includes depositing a second electrically conductive material. The second electrically conductive material extends beyond the boundary trench. The method further includes removing the sacrificial layer through etch openings and forming a cavity below the second electrically conductive material. The first electrically conductive material defines a portion of a sidewall boundary of the cavity.
Abstract translation: 用于形成悬浮膜的方法的实施例包括在牺牲层之上和边界沟槽内沉积第一导电材料。 第一导电材料在边界沟槽上方形成角部过渡部分。 该方法还包括去除第一导电材料的一部分，其去除第一导电材料的不均匀的形貌的至少一部分。 该方法还包括沉积第二导电材料。 第二导电材料延伸超过边界沟槽。 该方法还包括通过蚀刻开口移除牺牲层并在第二导电材料下方形成空腔。 第一导电材料限定空腔的侧壁边界的一部分。
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13.发明申请METHOD FOR MANUFACTURING A PROTECTIVE LAYER AGAINST HF ETCHING, SEMICONDUCTOR DEVICE PROVIDED WITH THE PROTECTIVE LAYER AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE 审中-公开用于制造抗蚀层的保护层的方法，用保护层提供的半导体器件及制造半导体器件的方法公开(公告)号：US20160130140A1
公开(公告)日：2016-05-12
申请号：US14982380
申请日：2015-12-29
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Stefano LOSA , Raffaella PEZZUTO , Roberto CAMPEDELLI , Matteo PERLETTI , Luigi ESPOSITO , Mikel Azpeitia URQUIA
IPC: B81C1/00
CPC classification number: H01L21/02178 , B81B7/0032 , B81B2201/0235 , B81B2201/0242 , B81C1/00595 , B81C1/00801 , B81C2201/014 , B81C2201/053 , H01L21/0228
Abstract: A method for manufacturing a protective layer for protecting an intermediate structural layer against etching with hydrofluoric acid, the intermediate structural layer being made of a material that can be etched or damaged by hydrofluoric acid, the method comprising the steps of: forming a first layer of aluminium oxide, by atomic layer deposition, on the intermediate structural layer; performing a thermal crystallization process on the first layer of aluminium oxide, forming a first intermediate protective layer; forming a second layer of aluminium oxide, by atomic layer deposition, above the first intermediate protective layer; and performing a thermal crystallization process on the second layer of aluminium oxide, forming a second intermediate protective layer and thereby completing the formation of the protective layer. The method for forming the protective layer can be used, for example, during the manufacturing steps of an inertial sensor such as a gyroscope or an accelerometer.
Abstract translation: 一种用于制造用于保护中间结构层以防止用氢氟酸蚀刻的保护层的方法，所述中间结构层由可被氢氟酸蚀刻或损坏的材料制成，所述方法包括以下步骤：形成第一层 氧化铝，通过原子层沉积在中间结构层上; 在第一氧化铝层上进行热结晶处理，形成第一中间保护层; 通过原子层沉积在第一中间保护层之上形成第二层氧化铝; 并在第二氧化铝层上进行热结晶处理，形成第二中间保护层，从而完成保护层的形成。 形成保护层的方法可以用于例如陀螺仪或加速度计等惯性传感器的制造步骤。
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公开(公告)号：US09267857B2
公开(公告)日：2016-02-23
申请号：US14543074
申请日：2014-11-17
Applicant: Honeywell International Inc.
Inventor： Carl Stewart , Richard Davis , Gilberto Morales
CPC classification number: B81C1/00158 , B81B3/0021 , B81B3/007 , B81B2201/0264 , B81B2203/0127 , B81C2201/014 , B81C2201/0198 , B81C2203/0728 , G01L7/08 , G01L9/0042 , G01L9/0044 , G01L9/0047 , G01L9/0054 , G01L9/0055
Abstract: A pressure sensor having a diaphragm having a boss with a pattern. The diaphragm having a boss may be regarded as a bossed diaphragm. The bossed diaphragm may have higher sensitivity than a flat plate diaphragm having the same area as the bossed diaphragm. The bossed diaphragm may incorporate a simple cross pattern that can further improve the sensitivity and linearity of a pressure response of the diaphragm at low pressures. Reduction of sharp edges and corners of the boss and its legs around the periphery of the diaphragm may reduce high stress points and thus increase the burst pressure rating of the bossed diaphragm.
Abstract translation: 一种压力传感器，具有具有带图案的凸台的隔膜。 具有凸台的隔膜可以被认为是凸起的隔膜。 凸起的隔膜可能具有比具有与凸起隔膜相同面积的平板隔膜更高的灵敏度。 凸起的隔膜可以包括简单的交叉图案，其可以进一步提高隔膜在低压下的压力响应的灵敏度和线性。 凸起及其围绕隔膜周边的腿的尖锐边缘和拐角的减小可能会降低高应力点，从而提高凸起隔膜的爆破压力等级。
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公开(公告)号：US20160023893A1
公开(公告)日：2016-01-28
申请号：US14444921
申请日：2014-07-28
Applicant: ams International AG
Inventor： Willem Besling , Remco Henricus Wilhelmus Pijnenburg , Casper van der Avoort , Marten Oldsen , Martijn Goossens
CPC classification number: B81C1/00158 , B81C1/00246 , B81C2201/014 , G01L9/0042 , G01L9/0072 , G01L9/0073 , G01L9/12 , H01L29/84
Abstract: Embodiments of a method for forming a suspended membrane include depositing a first electrically conductive material above a sacrificial layer and within a boundary trench. The first electrically conductive material forms a corner transition portion above the boundary trench. The method further includes removing a portion of the first electrically conductive material that removes at least a portion of uneven topography of the first electrically conductive material. The method further includes depositing a second electrically conductive material. The second electrically conductive material extends beyond the boundary trench. The method further includes removing the sacrificial layer through etch openings and forming a cavity below the second electrically conductive material. The first electrically conductive material defines a portion of a sidewall boundary of the cavity.
Abstract translation: 用于形成悬浮膜的方法的实施例包括在牺牲层之上和边界沟槽内沉积第一导电材料。 第一导电材料在边界沟槽上方形成角部过渡部分。 该方法还包括去除第一导电材料的一部分，其去除第一导电材料的不均匀的形貌的至少一部分。 该方法还包括沉积第二导电材料。 第二导电材料延伸超过边界沟槽。 该方法还包括通过蚀刻开口移除牺牲层并在第二导电材料下方形成空腔。 第一导电材料限定空腔的侧壁边界的一部分。
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Patent Agency Ranking
公开(公告)号：US09156681B2
公开(公告)日：2015-10-13
申请号：US13963409
申请日：2013-08-09
Applicant: DONGBU HITEK CO., LTD.
Inventor： Chung Kyung Jung , Ki Jun Yun , Oh Jin Jung , Sang Wook Ryu , Seong Hun Jeong , Sung Wook Joo
CPC classification number: B81C1/00015 , B81B3/0018 , B81B2201/018 , B81C1/00801 , B81C2201/014
Abstract: Method for manufacturing a semiconductor device includes the steps of forming a lower electrode pattern on a substrate, forming a first interlayer insulating layer on the lower electrode pattern, forming an upper electrode pattern on the first interlayer insulating layer, forming a second interlayer insulating layer on the upper electrode pattern, forming an etch blocking layer on a side of the upper electrode pattern, wherein the etch blocking layer passes through the first interlayer insulating layer, forming a cavity which exposes the side of the etch blocking layer by etching the second interlayer insulating layer, and forming a contact ball in the cavity.
Abstract translation: 制造半导体器件的方法包括以下步骤：在衬底上形成下电极图案，在下电极图案上形成第一层间绝缘层，在第一层间绝缘层上形成上电极图案，在第一层间绝缘层上形成第二层间绝缘层 所述上电极图案在所述上电极图案的一侧上形成蚀刻阻挡层，其中所述蚀刻阻挡层穿过所述第一层间绝缘层，形成通过蚀刻所述第二层间绝缘体而暴露所述蚀刻阻挡层侧的空腔 并且在空腔中形成接触球。
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17.发明申请Material quality, suspended material structures on lattice-mismatched substrates 有权材料质量，晶格失配衬底上的悬浮材料结构公开(公告)号：US20150102465A1
公开(公告)日：2015-04-16
申请号：US14512158
申请日：2014-10-10
Inventor： Robert Chen , James S. Harris, JR. , Suyog Gupta
IPC: H01L29/06 , H01L21/02 , H01L21/306 , H01L29/161 , H01L29/16
CPC classification number: H01L21/02535 , B81C1/00111 , B81C1/00571 , B81C2201/014 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/0245 , H01L21/02452 , H01L21/02507 , H01L21/02532 , H01L21/0262 , H01L21/3065 , H01L29/0665 , H01L29/0676 , H01L29/161 , H01S5/1075 , H01S5/3427
Abstract: Suspended structures are provided using selective etch technology. Such structures can be protected on all sides when the selective undercut etch is performed, thereby providing excellent control of feature geometry combined with superior material quality.
Abstract translation: 使用选择性蚀刻技术提供悬挂结构。 当执行选择性底切蚀刻时，可以在所有侧面上保护这种结构，从而提供优异的特征几何结合优良的材料质量控制。
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公开(公告)号：US08987059B2
公开(公告)日：2015-03-24
申请号：US13571264
申请日：2012-08-09
Applicant: Kai-Chih Liang , Chia-Hua Chu , Te-Hao Lee , Jiou-Kang Lee , Chung-Hsien Lin
Inventor： Kai-Chih Liang , Chia-Hua Chu , Te-Hao Lee , Jiou-Kang Lee , Chung-Hsien Lin
CPC classification number: B81C1/00515 , B81B7/0006 , B81B7/0077 , B81B2201/0235 , B81B2203/0315 , B81B2207/07 , B81B2207/095 , B81B2207/096 , B81C1/00293 , B81C1/00301 , B81C2201/0132 , B81C2201/014 , B81C2203/0109 , B81C2203/0118 , B81C2203/0145 , B81C2203/035 , H01L2224/11
Abstract: A microelectromechanical system (MEMS) device may include a MEMS structure over a first substrate. The MEMS structure comprises a movable element. Depositing a first conductive material over the first substrate and etching trenches in a second substrate. Filling the trenches with a second conductive material and depositing a third conductive material over the second conductive material and the second substrate. Bonding the first substrate and the second substrate and thinning a backside of the second substrate which exposes the second conductive material in the trenches.
Abstract translation: 微机电系统（MEMS）装置可以包括在第一基板上的MEMS结构。 MEMS结构包括可移动元件。 在第一衬底上沉积第一导电材料并蚀刻第二衬底中的沟槽。 用第二导电材料填充沟槽并在第二导电材料和第二衬底上沉积第三导电材料。 将第一基板和第二基板接合并使第二基板的背面变薄，从而在沟槽中露出第二导电材料。
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19.发明申请METHOD OF FABRICATING INTEGRATED STRUCTURE FOR MEMS DEVICE AND SEMICONDUCTOR DEVICE 有权制造MEMS器件和半导体器件的集成结构的方法公开(公告)号：US20150004732A1
公开(公告)日：2015-01-01
申请号：US14489495
申请日：2014-09-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Bang-Chiang Lan , Li-Hsun Ho , Wei-Cheng Wu , Hui-Min Wu , Min Chen , Tzung-I Su , Chien-Hsin Huang
IPC: B81C1/00
CPC classification number: B81C1/00246 , B81C1/00801 , B81C2201/014 , B81C2203/0714 , B81C2203/0742 , B81C2203/0792 , H01L27/0688
Abstract: A method of fabricating an integrated structure for MEMS device and semiconductor device comprises steps of: providing a substrate having a transistor thereon in a semiconductor device region and a first MEMS component thereon in a MEMS region; performing a interconnect process on the substrate in the semiconductor device region to form a plurality of first dielectric layers, at least a conductive plug and at least a conductive layer in the first dielectric layers; forming a plurality of second dielectric layers and an etch stopping device in the second dielectric layers on the substrate in a etch stopping device region; forming a plurality of third dielectric layers and at least a second MEMS component in the third dielectric layers on the substrate in the MEMS region; and performing an etching process to remove the third dielectric layers in the MEMS region.
Abstract translation: 制造用于MEMS器件和半导体器件的集成结构的方法包括以下步骤：在半导体器件区域中提供其上具有晶体管的衬底及其中的MEMS区域中的第一MEMS部件; 在所述半导体器件区域中的所述衬底上执行互连处理，以形成多个第一电介质层，所述第一介电层中的至少导电插塞和至少导电层; 在蚀刻停止装置区域中在衬底上的第二介电层中形成多个第二电介质层和蚀刻停止装置; 在MEMS区域中的衬底上的第三电介质层中形成多个第三电介质层和至少第二MEMS部件; 并执行蚀刻工艺以去除MEMS区域中的第三介电层。
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公开(公告)号：US08658452B2
公开(公告)日：2014-02-25
申请号：US13003328
申请日：2009-07-08
Applicant: Mourad El-Gamal , Frederic Nabki , Paul-Vahe Cicek
Inventor： Mourad El-Gamal , Frederic Nabki , Paul-Vahe Cicek
CPC classification number: B81C1/00666 , B81B3/0021 , B81B7/008 , B81B2201/01 , B81B2201/0235 , B81B2201/0271 , B81B2201/03 , B81B2207/015 , B81B2207/03 , B81C1/00063 , B81C1/00246 , B81C1/00396 , B81C1/00587 , B81C2201/014 , B81C2201/0169 , B81C2201/0174 , B81C2203/0721 , B81C2203/0735
Abstract: A method of providing microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is provided. The method providing for processes and manufacturing sequences limiting the maximum exposure of an integrated circuit upon which the MEMS is manufactured to below 350° C., and potentially to below 250° C., thereby allowing direct manufacturing of the MEMS devices onto electronics, such as Si CMOS circuits. The method further providing for the provisioning of MEMS devices with multiple non-conductive structural layers such as silicon carbide separated with small lateral gaps. Such silicon carbide structures offering enhanced material properties, increased environmental and chemical resilience whilst also allowing novel designs to be implemented taking advantage of the non-conductive material of the structural layer. The use of silicon carbide being beneficial within the formation of MEMS elements such as motors, gears, rotors, translation drives, etc where increased hardness reduces wear of such elements during operation.
Abstract translation: 提供了一种提供与硅CMOS电子器件兼容的微机电结构（MEMS）的方法。 该方法提供了将MEMS制造的集成电路的最大曝光限制在低于350℃并可能低于250℃的工艺和制造顺序，从而允许将MEMS器件直接制造到电子器件上，例如 作为Si CMOS电路。 该方法进一步提供具有多个非导电结构层的MEMS器件，例如用小的侧向间隙分离的碳化硅。 这种碳化硅结构提供增强的材料性能，增加环境和化学弹性，同时还允许利用结构层的非导电材料来实现新颖的设计。 在形成MEMS元件（例如马达，齿轮，转子，平移驱动器等）中使用碳化硅是有益的，其中增加的硬度降低了操作期间这些元件的磨损。
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