公开(公告)号：US09379021B2

公开(公告)日：2016-06-28

申请号：US14505167

申请日：2014-10-02

Applicant: Applied Materials, Inc.

Inventor： Ellie Y. Yieh ,  Ludovic Godet ,  Srinivas D. Nemani

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/302 ,  H01L21/461 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/28 ,  H01L21/04 ,  H01L21/225 ,  H01L21/3115 ,  H01L21/223

CPC classification number: H01L21/823462 ,  H01L21/0415 ,  H01L21/046 ,  H01L21/2236 ,  H01L21/2253 ,  H01L21/28185 ,  H01L21/31155 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/785

Abstract: Embodiments described herein generally relate to methods for forming gate structures. Various processes may be performed on a gate dielectric material to reduce the K value of the dielectric material. The gate dielectric having a reduced K value may provide for reduced parasitic capacitance and an overall reduced capacitance. The gate dielectric may be modified without thermodynamic constraint.

Abstract translation: 本文描述的实施例通常涉及用于形成栅极结构的方法。 可以在栅极电介质材料上进行各种工艺以降低电介质材料的K值。 具有减小的K值的栅极电介质可以提供减小的寄生电容和整体减小的电容。 可以在没有热力学约束的情况下修改栅极电介质。

公开(公告)号：US09368370B2

公开(公告)日：2016-06-14

申请号：US14642340

申请日：2015-03-09

Applicant: Applied Materials, Inc.

Inventor： Sergey G. Belostotskiy ,  Chinh Dinh ,  Qingjun Zhou ,  Srinivas D. Nemani ,  Andrew Nguyen

IPC: H01L21/302 ,  H01L21/311 ,  H01L21/263 ,  H01J37/32

CPC classification number: H01L21/31116 ,  H01J37/32091 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/3244 ,  H01L21/263

Abstract: A method for etching a dielectric layer disposed on a substrate is provided. The method includes de-chucking the substrate from an electrostatic chuck in an etching processing chamber, and cyclically etching the dielectric layer while the substrate is de-chucked from the electrostatic chuck. The cyclical etching includes remotely generating a plasma in an etching gas mixture supplied into the etching processing chamber to etch the dielectric layer disposed on the substrate at a first temperature. Etching the dielectric layer generates etch byproducts. The cyclical etching also includes vertically moving the substrate towards a gas distribution plate in the etching processing chamber, and flowing a sublimation gas from the gas distribution plate towards the substrate to sublimate the etch byproducts. The sublimation is performed at a second temperature, wherein the second temperature is greater than the first temperature.

Abstract translation: 提供了一种用于蚀刻设置在基板上的电介质层的方法。 该方法包括在蚀刻处理室中从静电卡盘取下基板，并在基板从静电卡盘脱卡的同时循环蚀刻电介质层。 循环蚀刻包括在提供到蚀刻处理室中的蚀刻气体混合物中远程产生等离子体，以在第一温度下蚀刻设置在基板上的电介质层。 蚀刻介电层产生蚀刻副产物。 循环蚀刻还包括将衬底垂直移动到蚀刻处理室中的气体分配板，并且使升华气体从气体分配板朝向衬底流动以升华蚀刻副产物。 升华在第二温度下进行，其中第二温度大于第一温度。

公开(公告)号：US09305796B2

公开(公告)日：2016-04-05

申请号：US14533389

申请日：2014-11-05

Applicant: APPLIED MATERIALS, INC.

Inventor： Sukti Chatterjee ,  Srinivas D. Nemani

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/3105

CPC classification number: H01L21/3065 ,  H01J2237/334 ,  H01L21/0234 ,  H01L21/02532 ,  H01L21/30621 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/67207

Abstract: Methods for etching silicon using hydrogen radicals in a hot wire chemical vapor deposition process are provided herein. In some embodiments, a method of processing a substrate having a crystalline silicon layer atop the substrate and a patterned masking layer atop the crystalline silicon layer exposing portions of the crystalline silicon layer; the method may include (a) exposing the substrate to a plasma formed from an inert gas wherein ions from the plasma amorphize a first part of the exposed portions of the crystalline silicon layer; and (b) exposing the substrate to hydrogen radicals generated from a process gas comprising a hydrogen-containing gas in a hot wire chemical vapor deposition (HWCVD) process chamber to etch the amorphized first part of the exposed portion of the crystalline silicon layer.

Abstract translation: 本文提供了在热线化学气相沉积工艺中使用氢自由基蚀刻硅的方法。 在一些实施例中，一种处理在衬底上方具有晶体硅层的衬底的方法以及暴露晶体硅层部分的晶体硅层顶部的图案化掩模层; 该方法可以包括（a）将衬底暴露于由惰性气体形成的等离子体，其中来自等离子体的离子将晶体硅层的暴露部分的第一部分非晶化; 和（b）将基底暴露于在热线化学气相沉积（HWCVD）处理室中由包含含氢气体的工艺气体产生的氢自由基，以蚀刻晶体硅层的暴露部分的非晶化第一部分。

公开(公告)号：US09269590B2

公开(公告)日：2016-02-23

申请号：US14247035

申请日：2014-04-07

Applicant: Applied Materials, Inc.

Inventor： Olivier Luere ,  Sean S. Kang ,  Srinivas D. Nemani

IPC: H01L21/00 ,  H01L21/311 ,  H01L21/027 ,  H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32139

Abstract: Embodiments of the present invention pertain to methods of forming more symmetric spacers which may be used for self-aligned multi-patterning processes. A conformal spacer layer of spacer material is formed over mandrels patterned near the optical resolution of a photolithography system using a high-resolution photomask. A carbon-containing layer is further formed over the conformal spacer layer. The carbon-containing layer is anisotropically etched to expose the high points of the conformal spacer layer while retaining carbon side panels. The conformal spacer layer may then be etched to form spacers without the traditional skewing of the profile towards one side or the other.

Abstract translation: 本发明的实施例涉及形成更多对称间隔物的方法，其可用于自对准多图案化工艺。 在使用高分辨率光掩模的光刻系统的光学分辨率附近形成的心轴上形成间隔物材料的保形间隔层。 在保形间隔层上进一步形成含碳层。 各向异性蚀刻含碳层以暴露保形间隔层的高点，同时保留碳侧面板。 然后可以蚀刻保形间隔层以形成间隔物，而不会使轮廓朝向一侧或另一侧的传统倾斜。

公开(公告)号：US09257330B2

公开(公告)日：2016-02-09

申请号：US14483578

申请日：2014-09-11

Applicant: Applied Materials, Inc.

Inventor： Amit Chatterjee ,  Geetika Bajaj ,  Pramit Manna ,  He Ren ,  Tapash Chakraborty ,  Srinivas D. Nemani ,  Mehul Naik ,  Robert Jan visser ,  Abhijit Basu Mallick

IPC: H01L21/68 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76834 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76838 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of depositing thin, low dielectric constant layers that are effective diffusion barriers on metal interconnects of semiconductor circuits are described. A self-assembled monolayer (SAM) of molecules each having a head moiety and a tail moiety are deposited on the metal. The SAM molecules self-align, wherein the head moiety is formulated to selectively bond to the metal layer leaving the tail moiety disposed at a distal end of the molecule. A dielectric layer is subsequently deposited on the SAM, chemically bonding to the tail moiety of the SAM molecules.

Abstract translation: 描述了在半导体电路的金属互连上沉积有效扩散阻挡层的薄的低介电常数层的方法。 每个具有头部和尾部的分子的自组装单层（SAM）沉积在金属上。 SAM分子自对准，其中头部部分被配制成选择性地键合到金属层，离开设置在分子远端的尾部。 随后在SAM上沉积介电层，化学键合到SAM分子的尾部。

公开(公告)号：US20150348902A1

公开(公告)日：2015-12-03

申请号：US14291466

申请日：2014-05-30

Applicant: Applied Materials, Inc.

Inventor： Mehul Naik ,  Paul F. Ma ,  Srinivas D. Nemani

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01J37/32091 ,  H01L21/02068 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76807 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Exemplary methods of forming a semiconductor structure may include etching a via through a semiconductor structure to expose a first circuit layer interconnect metal. The methods may include forming a layer of a material overlying the exposed first circuit layer interconnect metal. The methods may also include forming a barrier layer within the via having minimal coverage along the bottom of the via. The methods may additionally include forming a second circuit layer interconnect metal overlying the layer of material.

Abstract translation: 形成半导体结构的示例性方法可以包括通过半导体结构蚀刻通孔以暴露第一电路层互连金属。 所述方法可以包括形成覆盖暴露的第一电路层互连金属的材料层。 所述方法还可以包括在通孔内沿着通孔底部形成具有最小覆盖范围的阻挡层。 所述方法还可以包括形成覆盖在所述材料层上的第二电路层互连金属。

公开(公告)号：US09093389B2

公开(公告)日：2015-07-28

申请号：US14153246

申请日：2014-01-13

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. Nemani ,  Jeremiah T. Pender ,  Qingjun Zhou ,  Dmitry Lubomirsky ,  Sergey G. Belostotskiy

IPC: H01L21/311 ,  H01L21/321

CPC classification number: H01L21/31116 ,  H01L21/31111 ,  H01L21/32105

Abstract: Methods of patterning silicon nitride dielectric films are described. For example, a method of isotropically etching a dielectric film involves partially modifying exposed regions of a silicon nitride layer with an oxygen-based plasma process to provide a modified portion and an unmodified portion of the silicon nitride layer. The method also involves removing, selective to the unmodified portion, the modified portion of the silicon nitride layer with a second plasma process.

Abstract translation: 描述了图案化氮化硅介电膜的方法。 例如，各向同性蚀刻电介质膜的方法包括用氧基等离子体工艺部分地修饰氮化硅层的暴露区域，以提供氮化硅层的改性部分和未改性部分。 该方法还涉及通过第二等离子体处理来去除对未改性部分氮化硅层的改性部分的选择性。

公开(公告)号：US20150200042A1

公开(公告)日：2015-07-16

申请号：US14152978

申请日：2014-01-10

Applicant: Applied Materials, Inc.

Inventor： Mang Mang Ling ,  Sean S. Kang ,  Jeremiah T P Pender ,  Srinivas D. Nemani ,  Bradley J. Howard

IPC: H01B19/04 ,  H01J37/32

CPC classification number: H01B19/04 ,  H01J37/32082 ,  H01J37/32357 ,  H01J37/3244 ,  H01J2237/334

Abstract: A portion of the ultra-low k dielectric layer over a substrate is modified using a downstream plasma comprising a first chemistry. The modified portion of the ultra-low k dielectric layer is etched using the downstream plasma comprising a second chemistry. The downstream plasma is generated using a remote plasma source.

Abstract translation: 使用包含第一化学物质的下游等离子体改变衬底上的超低k电介质层的一部分。 使用包括第二化学物质的下游等离子体蚀刻超低k电介质层的改性部分。 使用远程等离子体源产生下游等离子体。