公开(公告)号：US20160209897A1

公开(公告)日：2016-07-21

申请号：US14980209

申请日：2015-12-28

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  DARIUS D. GASKINS

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/24 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30083 ,  G06F9/44505 ,  G06F9/5094 ,  G06F11/1423 ,  G06F11/3664 ,  G06F13/36 ,  G06F15/163 ,  G06F15/82 ,  Y02D10/14 ,  Y02D10/22

Abstract: A multi-die package for a microprocessor provides a power management synchronization system. The package has a plurality of dies. Each die has a plurality of cores, including a single master core. A plurality of sideband non-system-bus inter-die communication wires communicatively couple the dies to each other for a purpose of synchronizing power management. The master core of each die is configured to use one and only one of the inter-die communication wires to transmit power management synchronization messages to each of the other master cores. The master core of each die is also configured to receive power management synchronization messages from each of the other master cores via one or more inter-die communication wires. The cores use this system of inter-die communication wires to synchronize management of resources that affect both the performance and power consumption of the cores.

Abstract translation: 用于微处理器的多管芯封装提供电源管理同步系统。 该封装具有多个管芯。 每个管芯具有多个芯，包括单个母芯。 为了同步电源管理的目的，多个边带非系统总线芯片间通信线通信地将管芯彼此连接。 每个管芯的主核心被配置为使用芯片间通信线中的一个且仅一个将功率管理同步消息发送到每个其他主核。 每个裸片的主核心还被配置为经由一个或多个芯片间通信线路从每个其他主核心接收功率管理同步消息。 内核使用这种芯片间通信线系统来同步影响内核性能和功耗的资源管理。

公开(公告)号：US09395802B2

公开(公告)日：2016-07-19

申请号：US14285448

申请日：2014-05-22

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain ,  Stephan Gaskins

IPC: G06F1/32 ,  G06F12/12 ,  G06F12/08 ,  G06F11/10 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00 ,  G11C29/44

CPC classification number: G06F3/0631 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/10 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0866 ,  G06F12/12 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/283 ,  G06F2212/313 ,  G06F2212/601 ,  G06F2212/608 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C29/787 ,  G11C2029/4402

Abstract: An apparatus includes a fuse array and a stores. The fuse array is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores. Each of the plurality of cores has sleep logic. The sleep logic is configured to subsequently access a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following a power gating event.

Abstract translation: 一种装置包括熔丝阵列和商店。 保险丝阵列用多个核心的压缩配置数据编程。 存储器耦合到多个核心，并且包括多个子存储器，每个子存储器对应于多个核心中的每一个，多个核心中的一个核心在上电/复位时访问半导体熔丝阵列以读取，以及 对压缩的配置数据进行解压缩，并且在多个子存储器中的多个核心的每个内存储一个或多个高速缓存存储器的多个解压配置数据集。 多个核心中的每一个具有睡眠逻辑。 睡眠逻辑被配置为随后访问多个子商店中的每一个的对应的一个，以检索并使用解压配置数据集来初始化电源门控事件之后的一个或多个高速缓存。

公开(公告)号：US20160202980A1

公开(公告)日：2016-07-14

申请号：US14963134

申请日：2015-12-08

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  RODNEY E. HOOKER

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/3016 ,  G06F9/30025 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/4401 ,  G06F12/0875 ,  G06F2212/452

Abstract: A microprocessor natively translates and executes instructions of both the x86 instruction set architecture (ISA) and the Advanced RISC Machines (ARM) ISA. An instruction formatter extracts distinct ARM instruction bytes from a stream of instruction bytes received from an instruction cache and formats them. ARM and x86 instruction length decoders decode ARM and x86 instruction bytes, respectively, and determine instruction lengths of ARM and x86 instructions. An instruction translator translates the formatted x86 ISA and ARM ISA instructions into microinstructions of a unified microinstruction set architecture of the microprocessor. An execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions.

Abstract translation: 微处理器本地翻译和执行x86指令集架构（ISA）和高级RISC机器（ARM）ISA的指令。 指令格式化器从指令高速缓存接收的指令字节流中提取不同的ARM指令字节，并对其进行格式化。 ARM和x86指令长度解码器分别解码ARM和x86指令字节，并确定ARM和x86指令的指令长度。 指令翻译器将格式化的x86 ISA和ARM ISA指令转换为微处理器的统一微指令集架构的微指令。 执行流水线执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。

公开(公告)号：US09389863B2

公开(公告)日：2016-07-12

申请号：US14522512

申请日：2014-10-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

IPC: G06F9/30 ,  G06F11/07

CPC classification number: G06F9/30145 ,  G06F9/30014 ,  G06F9/30076 ,  G06F9/30185 ,  G06F9/30189 ,  G06F11/0721 ,  G06F11/0793

Abstract: A processor includes a decoder that decodes an instruction that instructs the processor to perform subsequent computations in an approximate manner and a functional unit that performs the subsequent computations in the approximate manner in response to the instruction. An instruction instructs the processor to clear an error amount associated with a value stored in a general purpose register of the processor. The error amount indicates an amount of error associated with a result of a computation performed by the processor in an approximate manner. The processor also clears the error amount in response to the instruction. Another instruction specifies a computation to be performed and includes a prefix that indicates the processor is to perform the computation in an approximate manner. The functional unit performs the computation specified by the instruction in the approximate manner specified by the prefix.

Abstract translation: 一种处理器包括一个译码器，该解码器解码指示处理器以近似方式执行后续计算的指令，以及响应该指令以近似方式执行后续计算的功能单元。 指令指示处理器清除与存储在处理器的通用寄存器中的值相关联的错误量。 错误量表示与处理器以近似的方式执行的计算结果相关联的错误量。 处理器还会根据指令清除错误量。 另一个指令指定要执行的计算，并且包括指示处理器以近似的方式执行计算的前缀。 功能单元以由前缀指定的近似方式执行由指令指定的计算。

公开(公告)号：US20160196703A1

公开(公告)日：2016-07-07

申请号：US15000205

申请日：2016-01-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Jui-Cheng JEAN

IPC: G07C9/00 ,  G06K9/00 ,  H04N7/18

CPC classification number: G06K9/00288 ,  H04N7/186

Abstract: The content provides a smart door system and identification system. The identification system includes a Bluetooth low energy (BLE) signal broadcasting apparatus, a signal processing apparatus, a wireless signal receiving apparatus and a server. The signal processing apparatus receives a BLE signal broadcasted by the BLE signal broadcasting apparatus and transmits identification information to the wireless signal receiving apparatus by wireless communication. The server stores verification information and determines what the signal processing apparatus represents in accordance with a relationship between the verification information and the identification information received from the wireless signal receiving apparatus.

Abstract translation: 内容提供智能门系统和识别系统。 识别系统包括蓝牙低能量（BLE）信号广播装置，信号处理装置，无线信号接收装置和服务器。 信号处理装置接收由BLE信号广播装置广播的BLE信号，并通过无线通信向无线信号接收装置发送识别信息。 服务器存储验证信息，并根据验证信息和从无线信号接收设备接收到的识别信息之间的关系确定信号处理设备所代表的内容。

公开(公告)号：US09377833B2

公开(公告)日：2016-06-28

申请号：US13935904

申请日：2013-07-05

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Shuang-Shuang Qin ,  Xiaolu Yang ,  Chin-Hwaun Wu

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3296 ,  Y02D10/172 ,  Y02D50/20

Abstract: A power management method for use in an electronic system is provided. The electronic system has a processor and a power management unit. The method has the steps of: when the processor has entered a low power state and an awakening event occurs, calculating a staying time from the time point the processor enters the low power state till the time point the awakening event occurs, wherein the operation voltage of the processor is at a first voltage level in the low power state; and when the processing starts to exit the low power state according to the awakening event, determining a wait time, during which the operation voltage of the processor is recovered to a second voltage level of a working state from the first voltage level, wherein the first voltage level is lower than the second voltage level.

Abstract translation: 提供了一种用于电子系统的电源管理方法。 电子系统具有处理器和电源管理单元。 该方法具有以下步骤：当处理器进入低功率状态并发生唤醒事件时，计算从处理器进入低功率状态的时间点到发生觉醒事件的时间点的停留时间，其中操作电压 处于低功率状态的第一电压电平; 并且当所述处理根据所述唤醒事件开始退出所述低功率状态时，确定所述处理器的操作电压从所述第一电压电平恢复到工作状态的第二电压电平的等待时间，其中所述第一 电压电平低于第二电压电平。

公开(公告)号：US20160110289A1

公开(公告)日：2016-04-21

申请号：US14624981

申请日：2015-02-18

Applicant: VIA TECHNOLOGIES, INC.

Inventor： RODNEY E. HOOKER ,  ALBERT J. LOPER ,  JOHN MICHAEL GREER ,  MEERA RAMANI-AUGUSTIN

IPC: G06F12/08 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F9/30047 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/30109 ,  G06F9/3802 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0862 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/6022 ,  G06F2212/6024

Abstract: A hardware data prefetcher is comprised in a memory access agent, wherein the memory access agent is one of a plurality of memory access agents that share a memory. The hardware data prefetcher includes a prefetch trait that is initially either exclusive or shared. The hardware data prefetcher also includes a prefetch module that performs hardware prefetches from a memory block of the shared memory using the prefetch trait. The hardware data prefetcher also includes an update module that performs analysis of accesses to the memory block by the plurality of memory access agents and, based on the analysis, dynamically updates the prefetch trait to either exclusive or shared while the prefetch module performs hardware prefetches from the memory block using the prefetch trait.

Abstract translation: 硬件数据预取器包括在存储器访问代理中，其中存储器访问代理是共享存储器的多个存储器访问代理之一。 硬件数据预取器包括最初是独占的或共享的预取特征。 硬件数据预取器还包括预取模块，其使用预取特征从共享存储器的存储器块执行硬件预取。 硬件数据预取器还包括更新模块，其执行由多个存储器访问代理对存储块的访问的分析，并且基于该分析，在预取模块执行硬件预取从 内存块使用预取特征。

公开(公告)号：US20160104009A1

公开(公告)日：2016-04-14

申请号：US14884502

申请日：2015-10-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  BRENT BEAN ,  THOMAS A. CRISPIN

IPC: G06F21/72 ,  H04L9/08 ,  G06F21/74 ,  G06F9/30

CPC classification number: G06F21/72 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/602 ,  G06F21/71 ,  G06F21/74 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A microprocessor and method are provided for securely decrypting and executing encrypted instructions within a microprocessor. A plurality of master keys are stored in a secure memory. Encrypted instructions are fetched from an instruction cache. A set of one or more master keys are selected from the secure memory based upon an encrypted instruction fetch address. The selected set of master keys or a decryption key derived therefrom is used to decrypt the encrypted instructions fetched from the instruction cache. The decrypted instructions are then securely executed within the microprocessor. In one implementation, the master keys are intervolved with each other to produce a new decryption key with every fetch quantum. Moreover, a new set of master keys is selected with every new block of instructions.

Abstract translation: 提供了微处理器和方法，用于在微处理器内安全解密和执行加密指令。 多个主密钥存储在安全存储器中。 从指令缓存中提取加密指令。 基于加密的指令提取地址从安全存储器中选择一组或多个主密钥。 所选择的一组主密钥或从其导出的解密密钥用于解密从指令高速缓存取出的加密指令。 然后在微处理器内安全地执行解密的指令。 在一个实现中，主密钥彼此相互交织以产生具有每个获取量子的新的解密密钥。 此外，每个新的指令块都选择一组新的主键。

公开(公告)号：US09298212B2

公开(公告)日：2016-03-29

申请号：US14143666

申请日：2013-12-30

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Darius D. Gaskins ,  G. Glenn Henry

IPC: G06F1/06 ,  G06F1/32

CPC classification number: G06F1/06 ,  G06F1/3296 ,  Y02D10/172

Abstract: Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a desired operating state of the core. Each core is also configured to receive a corresponding value from each other core sharing the applicable resource, and to calculate a composite value compatible with the minimal needs of each core sharing the applicable resource. Each core is further configured to conditionally drive the composite value off core to the applicable resource based on whether the core is designated as a master core for purposes of controlling or coordinating the applicable resource. The composite value is supplied to the applicable shared resource without using any active logic outside the plurality of cores.

Abstract translation: 微处理器具有分散逻辑和相关联的方法，用于将功率相关的操作状态（例如期望的电压和频率比）指示给共享的微处理器功率资源，例如电压调节器模块（VRM）和锁相环（PLL）。 每个核心被配置为产生一个值以指示所述核心的期望操作状态。 每个核心还被配置为从彼此分配可用资源的核心接收相应的值，并且计算与共享可应用资源的每个核心的最小需求兼容的复合值。 每个核心还被配置为基于是否将核心指定为主核以有条件地将核心的复合值驱动到适用的资源，以便控制或协调适用的资源。 复合值被提供给可应用的共享资源，而不使用多个核之外的任何活动逻辑。

公开(公告)号：US09251083B2

公开(公告)日：2016-02-02

申请号：US13792428

申请日：2013-03-11

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  John Michael Greer

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6026

Abstract: A microprocessor includes a first and second hardware data prefetchers configured to prefetch data into the microprocessor according to first and second respective algorithms, which are different. The second prefetcher is configured to detect a memory access pattern within a memory region and responsively prefetch data from the memory region according the second algorithm. The second prefetcher is further configured to provide to the first prefetcher a descriptor of the memory region. The first prefetcher is configured to stop prefetching data from the memory region in response to receiving the descriptor of the memory region from the second prefetcher. The second prefetcher also provides to the first prefetcher a communication to resume prefetching data from the memory region, such as when the second prefetcher subsequently detects that a predetermined number of memory accesses to the memory region are not in the memory access pattern.

Abstract translation: 微处理器包括第一和第二硬件数据预取器，其被配置为根据不同的第一和第二相应算法将数据预取入微处理器。 第二预取器被配置为检测存储器区域内的存储器访问模式，并且根据第二算法响应地从存储器区域预取数据。 第二预取器还被配置为向第一预取器提供存储器区域的描述符。 响应于从第二预取器接收到存储器区域的描述符，第一预取器被配置为停止从存储器区域预取数据。 第二预取器还向第一预取器提供通信以恢复从存储器区域预取数据，例如当第二预取器随后检测到对存储器区域的预定数量的存储器访问不在存储器访问模式中时。