公开(公告)号：US5789811A

公开(公告)日：1998-08-04

申请号：US725735

申请日：1996-10-04

Applicant: Chok J. Chia ,  Patrick Variot

Inventor： Chok J. Chia ,  Patrick Variot

IPC: H01L23/12 ,  H01L23/24 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H05K3/34 ,  H01L23/02

CPC classification number: H01L23/24 ,  H01L23/3128 ,  H01L23/49531 ,  H01L23/49811 ,  H01L23/49816 ,  H05K3/341 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H05K2201/10659 ,  H05K2201/10681 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/613

Abstract: A surface mounted integrated circuit die package includes a group of peripheral leads extending laterally outwardly from the perimeter of the package and also includes an array of solder balls on the bottom of the package. The arrangement provides for a greater number of input/output connections to a die package by utilizing both peripheral leads and a ball grid array without requiring increases in package size or a reduction in the width of electrically conductive interconnections.

公开(公告)号：US5648679A

公开(公告)日：1997-07-15

申请号：US511395

申请日：1995-08-04

Applicant: Satya Chillara ,  Shahram Mostafazadeh

Inventor： Satya Chillara ,  Shahram Mostafazadeh

IPC: H01L23/31 ,  H01L23/498 ,  H05K3/34 ,  H01L23/02

CPC classification number: H01L23/4985 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/49 ,  H05K3/341 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/613

Abstract: An integrated circuit assembly includes a dielectric flex tape substrate defining a predetermined array of electrically conductive traces and an array of solder balls or solder columns electrically connected to the bottom surface of the flex tape substrate and the traces. An integrated circuit die having a series of input/output pads is supported on the substrate. In one embodiment, a plurality of electrically conductive leads are supported by the flex tape substrate in electrical isolation from and over the conductive traces. A first and second series of bonding wires electrically connect certain ones of the input/output terminals on the integrated circuit die to the electrically conductive leads and conductive traces, respectively. In other embodiments, one or more electrically isolated conductive layers are supported by the dielectric flex tape substrate over the traces and electrically conductive leads. The integrated circuit package assembly, in accordance with any of these embodiments, provides a very high density electrical interconnection arrangement for the integrated circuit die while retaining a small package footprint.

Abstract translation: 集成电路组件包括限定预定数量的导电迹线的电介质柔性带衬底和电连接到柔性带衬底和迹线的底表面的焊球或焊料柱的阵列。 具有一系列输入/输出焊盘的集成电路管芯被支撑在衬底上。 在一个实施例中，多个导电引线由导电迹线与导电迹线电绝缘支撑在柔性带基片上。 第一和第二系列接合线分别将集成电路管芯上的某些输入/输出端子电连接到导电引线和导电迹线。 在其他实施例中，一个或多个电绝缘导电层由电介质柔性带基板支撑在迹线和导电引线上。 根据这些实施例中的任何一个的集成电路封装组件为集成电路管芯提供非常高密度的电互连布置，同时保持小的封装封装。

公开(公告)号：US5569955A

公开(公告)日：1996-10-29

申请号：US406726

申请日：1995-03-20

Applicant: Satya Chillara ,  Shahram Mostafazadeh

Inventor： Satya Chillara ,  Shahram Mostafazadeh

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L23/49861 ,  H01L23/3121 ,  H01L23/49517 ,  H01L23/4985 ,  H01L24/49 ,  H05K3/341 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/613

Abstract: An integrated circuit assembly is disclosed herein. The assembly includes a dielectric substrate defining a predetermined array of electrically conductive traces and an array of solder balls electrically connected to the traces. An integrated circuit chip having a series of input/output pads is supported on the substrate. In one embodiment, a plurality of leadframe leads are supported by the substrate in electrical isolation from and over the conductive traces. First and second series of bonding wires electrically connect certain ones of the input/output pads on the IC chip to the leadframe leads and conductive traces. In other embodiments, one or more electrically isolated conductive layers are supported by the dielectric substrate over the traces and leadframe leads. The integrated circuit assembly, in accordance with any of these embodiments, provides a very high density electrical interconnection arrangement for the IC chip while retaining a small package footprint.

公开(公告)号：US5521427A

公开(公告)日：1996-05-28

申请号：US340807

申请日：1994-11-17

Applicant: Chok J. Chia ,  Seng-Sooi Lim

Inventor： Chok J. Chia ,  Seng-Sooi Lim

IPC: H01L23/495 ,  H05K3/30 ,  H05K3/34 ,  H01L23/544

CPC classification number: H05K3/303 ,  H01L23/49541 ,  H01L2224/48091 ,  H01L2224/48247 ,  H05K2201/10303 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10962 ,  H05K2203/167 ,  H05K3/3421 ,  Y02P70/613 ,  Y10S438/975 ,  Y10T29/49121 ,  Y10T29/49133

Abstract: A packaged semiconductor device, leadframe for making same, and method of mounting same to a printed circuit board are described. The device has a body, and a plurality of leads extending from the body. One or more alignment features are formed on the exterior of the package body, for maintaining precise alignment of the device with respect to a printed wiring board. The alignment feature is a tab formed as part of portion of the leadframe external to the package body. The tab may have various shapes, and may be provided with a hole for registering with a pin on an underlying substrate, such as a printed wiring board. The pin and the tab may be electrically connected.

Abstract translation: 描述了一种封装的半导体器件，用于制造其的引线框，以及将其安装到印刷电路板的方法。 该装置具有主体和从主体延伸的多个引线。 一个或多个对准特征形成在包装体的外部上，以保持装置相对于印刷线路板的精确对准。 对准特征是形成为包装体外部的引线框架的一部分的突片。 突片可以具有各种形状，并且可以设置有用于与诸如印刷线路板的下面的基板上的销对准的孔。 引脚和突片可以电连接。

公开(公告)号：US5451815A

公开(公告)日：1995-09-19

申请号：US215614

申请日：1994-03-22

Applicant: Norio Taniguchi ,  Kazuto Tsuji ,  Junichi Kasai ,  Michio Sono

Inventor： Norio Taniguchi ,  Kazuto Tsuji ,  Junichi Kasai ,  Michio Sono

IPC: H01L23/04 ,  H01L23/12 ,  H01L23/498 ,  H05K3/30 ,  H05K3/34 ,  H01L23/48

CPC classification number: H05K3/303 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K2201/09781 ,  H05K2201/10454 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10696 ,  H05K3/3426 ,  Y02P70/613

Abstract: A semiconductor device includes vertical placement part for mounting the semiconductor device on a surface of a circuit board in a vertical position, and a connection part for making electrical connections between the circuit board and a semiconductor element. A stage is provided on which the semiconductor element is placed. The stage has supporting members causing the semiconductor device to vertically stand on the circuit board. Wiring boards, stacked on a side of the stage on which the semiconductor element is placed, have windows in which the semiconductor element is located. The vertical placement part includes wiring lines extending between edges of the wiring boards facing the circuit board and peripheries of the windows. The wiring lines have ends located in the vicinity of the edges of the wiring boards and have a shape enabling the semiconductor device to be mounted on the circuit board.

Abstract translation: 半导体器件包括用于将半导体器件安装在垂直位置的电路​​板的表面上的垂直放置部分和用于在电路板和半导体元件之间进行电连接的连接部分。 提供放置半导体元件的平台。 舞台具有使半导体器件垂直站立在电路板上的支撑构件。 堆叠在其上放置半导体元件的台的一侧的布线板具有半导体元件所在的窗口。 垂直放置部分包括在布线板的面向电路板的边缘和窗口的周边之间延伸的布线。 布线具有位于布线板的边缘附近的端部，并且具有能够将半导体器件安装在电路板上的形状。

公开(公告)号：US5442230A

公开(公告)日：1995-08-15

申请号：US307270

申请日：1994-09-16

Applicant: Satya Chillara ,  Shahram Mostafazadeh

Inventor： Satya Chillara ,  Shahram Mostafazadeh

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H05K3/34 ,  H01L23/02

CPC classification number: H05K3/341 ,  H01L23/3121 ,  H01L23/49517 ,  H01L23/4985 ,  H01L23/49861 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/613

Abstract: An integrated circuit assembly is disclosed herein. The assembly includes a dielectric substrate defining a predetermined array of electrically conductive traces and an array of solder balls electrically connected to the traces. An integrated circuit chip having a series of input/output pads is supported on the substrate. In one embodiment, a plurality of leadframe leads are supported by the substrate in electrical isolation from and over the conductive traces. First and second series of bonding wires electrically connect certain ones of the input/output pads on the IC chip to the leadframe leads and conductive traces. In other embodiments, one or more electrically isolated conductive layers are supported by the dielectric substrate over the traces and leadframe leads. The integrated circuit assembly, in accordance with any of these embodiments, provides a very high density electrical interconnection arrangement for the IC chip while retaining a small package footprint.

Abstract translation: 本文公开了集成电路组件。 组件包括限定预定阵列的导电迹线的电介质基片和电连接到迹线的焊球阵列。 具有一系列输入/输出焊盘的集成电路芯片被支撑在基板上。 在一个实施例中，多个引线框引线由导电迹线与导电迹线电隔离地由衬底支撑。 第一和第二系列接合线将IC芯片上的某些输入/输出焊盘电连接到引线框引线和导电迹线。 在其他实施例中，一个或多个电绝缘导电层由电介质基板支撑在迹线和引线框引线上。 根据这些实施例中的任何一个的集成电路组件为IC芯片提供非常高密度的电互连布置，同时保持小的封装封装。

公开(公告)号：US5430326A

公开(公告)日：1995-07-04

申请号：US238673

申请日：1994-05-05

Applicant: Shuji Miyashita

Inventor： Shuji Miyashita

IPC: H01L25/07 ,  H01L25/11 ,  H01L25/18 ,  H02M7/00 ,  H02M7/04 ,  H02M7/48 ,  H05K1/18 ,  H05K3/32 ,  H01L25/065 ,  H01L23/48

CPC classification number: H02M7/003 ,  H01L25/115 ,  H05K1/18 ,  H01L2924/0002 ,  H05K2201/10166 ,  H05K2201/10409 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K3/325

Abstract: A semiconductor device includes at least one semiconductor element contained in a casing, with main terminals and auxiliary terminals drawn from the semiconductor electrodes disposed on the upper face of the casing. The main terminals and the auxiliary terminals are arranged on the same plane at the same height without disposing partitions between the terminals so that the devices can be mounted on a printed wiring board on which the necessary conductor patterns for the main circuit have already been formed. In an alternative embodiment, the main terminals are arranged at a level slightly higher than the auxiliary terminals with the auxiliary terminals being surrounded by a supporting guide.

Abstract translation: 半导体器件包括容纳在壳体中的至少一个半导体元件，其中主端子和辅助端子从设置在壳体的上表面上的半导体电极拉出。 主端子和辅助端子以相同的高度布置在相同的平面上，而不在端子之间设置隔板，使得器件可以安装在已经形成了用于主电路的必要导体图案的印刷线路板上。 在替代实施例中，主端子被布置在略高于辅助端子的水平处，辅助端子被支撑引导件包围。

公开(公告)号：US5320541A

公开(公告)日：1994-06-14

申请号：US7935

申请日：1993-01-25

Applicant: Iosif Korsunsky ,  Dimitry G. Grabbe

Inventor： Iosif Korsunsky ,  Dimitry G. Grabbe

IPC: H01R12/50 ,  H01R12/57 ,  H01R12/58 ,  H01R12/71 ,  H01R12/73 ,  H05K1/11 ,  H05K3/34 ,  H05K3/42 ,  H01R23/70

CPC classification number: H05K3/3405 ,  H01R12/716 ,  H01R12/737 ,  H01R23/6873 ,  H01R12/57 ,  H01R12/585 ,  H05K1/117 ,  H05K2201/09163 ,  H05K2201/10189 ,  H05K2201/1034 ,  H05K2201/10401 ,  H05K2201/10659 ,  H05K2201/10916 ,  H05K3/429 ,  Y10T29/49149

Abstract: An electrical connector has first terminals which are surface mounted to respective sides of a substrate and second terminals which extend through an edge surface of the substrate to make electrical connection to an opening provided in the substrate. As the connector is mated to the edge of the substrate, the connector occupies a minimal space on the substrate.

Abstract translation: 电连接器具有表面安装到基板的相对侧的第一端子和延伸穿过基板的边缘表面的第二端子，以与设置在基板中的开口电连接。 当连接器配合到基板的边缘时，连接器占据基板上的最小空间。

公开(公告)号：US5305179A

公开(公告)日：1994-04-19

申请号：US899270

申请日：1992-06-16

Applicant: Michio Sono ,  Junichi Kasai ,  Kouji Saito ,  Kazuhiko Mitobe ,  Masanori Yoshimoto

Inventor： Michio Sono ,  Junichi Kasai ,  Kouji Saito ,  Kazuhiko Mitobe ,  Masanori Yoshimoto

IPC: H01L23/36 ,  H01L23/495 ,  H05K1/02 ,  H05K1/18 ,  H05K7/20

CPC classification number: H05K1/0203 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49582 ,  H05K1/181 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K2201/10166 ,  H05K2201/10454 ,  H05K2201/10469 ,  H05K2201/1053 ,  H05K2201/10659 ,  Y02P70/611

Abstract: A semiconductor device includes a semiconductor chip mounted in a resin package body. A plurality of interconnection leads are provided on the resin package body along a lower edge thereof and project outwardly from the lower edge. A heat dissipation lead is connected to the resin package body for dissipating heat generated by the semiconductor chip. The heat dissipation lead includes a plate of a heat conducting material having a stage part and a heat sink part, wherein the stage part is held inside the resin package body and supports the semiconductor chip thereon. The heat sink part projects outwardly from the resin package body and includes a part that extends in a downward direction. The heat sink part has a lower edge that is formed at a level substantially flush with the outer lead part of the interconnection leads such that the semiconductor device is held upright, when placed on a substrate, by the outer lead part of the interconnection leads and by the lower edge of the heat sink part of the heat dissipation lead.

Abstract translation: 半导体器件包括安装在树脂封装主体中的半导体芯片。 多个互连引线沿其下边缘设置在树脂封装主体上并且从下边缘向外突出。 散热引线连接到树脂封装体，用于散发由半导体芯片产生的热量。 散热引线包括具有台部和散热部的导热材料板，其中台部保持在树脂封装主体的内部并且在其上支撑半导体芯片。 散热部从树脂封装主体向外突出并包括向下延伸的部分。 散热部分具有下边缘，该下边缘形成在与互连引线的外部引线部分基本齐平的水平面处，使得半导体器件通过互连引线的外部引线部分放置在基板上时被保持为直立，并且 通过散热片的下缘部分散热引线。

公开(公告)号：US5199885A

公开(公告)日：1993-04-06

申请号：US873526

申请日：1992-04-21

Applicant: Iosif Korsunsky ,  Dimitry G. Grabbe

Inventor： Iosif Korsunsky ,  Dimitry G. Grabbe

IPC: H01R12/50 ,  H01R12/57 ,  H01R12/58 ,  H01R12/71 ,  H01R12/73 ,  H05K1/11 ,  H05K3/34 ,  H05K3/42

CPC classification number: H05K3/3405 ,  H01R12/716 ,  H01R12/737 ,  H01R23/6873 ,  H01R12/57 ,  H01R12/585 ,  H05K1/117 ,  H05K2201/09163 ,  H05K2201/10189 ,  H05K2201/1034 ,  H05K2201/10401 ,  H05K2201/10659 ,  H05K2201/10916 ,  H05K3/429 ,  Y10T29/49149

Abstract: An electrical connector has first terminals which are surface mounted to respective sides of a substrate and second terminals which extend through an edge surface of the substrate to make electrical connection to an opening provided in the substrate. As the connector is mated to the edge of the substrate, the connector occupies a minimal space on the substrate.

Abstract translation: 电连接器具有表面安装到基板的相对侧的第一端子和延伸穿过基板的边缘表面的第二端子，以与设置在基板中的开口电连接。 当连接器配合到基板的边缘时，连接器占据基板上的最小空间。