公开(公告)号：US06489571B1

公开(公告)日：2002-12-03

申请号：US09703199

申请日：2000-10-31

Applicant: Chok J. Chia ,  Qwai H. Low ,  Patrick Variot

Inventor： Chok J. Chia ,  Qwai H. Low ,  Patrick Variot

IPC: H05K109

CPC classification number: H01L23/3128 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A molded tape ball grid array package includes a molding compound and a tape substrate having a top surface for mounting a die thereon, a bottom surface for attaching solder balls, and vias for forming connections between the solder balls and the die wherein the molding compound surrounds the die and the tape substrate.

Abstract translation: 模塑带状球栅阵列封装包括模塑料和具有用于在其上安装模具的顶表面的带基材，用于附接焊球的底表面和用于形成焊球和模之间的连接的通孔，其中模塑料围绕 模具和胶带基材。

公开(公告)号：US6143586A

公开(公告)日：2000-11-07

申请号：US97882

申请日：1998-06-15

Applicant: Chok J. Chia ,  Patrick Variot ,  Qwai H. Low

Inventor： Chok J. Chia ,  Patrick Variot ,  Qwai H. Low

IPC: H01L23/60 ,  H01L21/44 ,  H01L21/331 ,  H01L21/336 ,  H01L21/48 ,  H01L21/50 ,  H01L21/82 ,  H01L31/479

CPC classification number: H01L23/60 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14

Abstract: An electrostatic protected integrated circuit (IC) substrate and a method of making an integrated circuit package with the electrostatic protected IC substrate includes an IC substrate, having a plurality of electrical traces formed on the top of the IC substrate with the electrical traces extending from an IC chip mounting area near the center to the periphery of the IC substrate. Electrically shorting the electrical traces together with a conductive material such as conductive tape or epoxy, thereby, protecting the IC substrate against the accumulation of static charges during the assembly of the IC chip on the IC substrate. The IC chip is mounted in the mounting area on the IC substrate and the conductive material is removed before final testing.

Abstract translation: 静电保护集成电路（IC）衬底和制造具有静电保护IC衬底的集成电路封装的方法包括IC衬底，其具有形成在IC衬底的顶部上的多个电迹线，电迹线从 IC芯片安装区域靠近IC基板周围的中心。 将导电电路与导电胶带或环氧树脂等导电材料电气短路，从而在集成电路芯片集成在IC基板上时，保护IC基板免受静电荷的积累。 IC芯片安装在IC基板上的安装区域，导电材料在最终测试之前被去除。

公开(公告)号：US5933710A

公开(公告)日：1999-08-03

申请号：US910608

申请日：1997-08-13

Applicant: Chok J. Chia ,  Patrick Variot

Inventor： Chok J. Chia ,  Patrick Variot

IPC: H01L23/12 ,  H01L23/24 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H05K3/34 ,  H01L21/44 ,  B23K31/02 ,  H01L23/48

CPC classification number: H01L23/24 ,  H01L23/3128 ,  H01L23/49531 ,  H01L23/49811 ,  H01L23/49816 ,  H05K3/341 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H05K2201/10659 ,  H05K2201/10681 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/613

Abstract: A surface mounted integrated circuit die package includes a group of peripheral leads extending laterally outwardly from the perimeter of the package and also includes an array of solder balls on the bottom of the package. The arrangement provides for a greater number of input/output connections to a die package by utilizing both peripheral leads and a ball grid array without requiring increases in package size or a reduction in the width of electrically conductive interconnections.

Abstract translation: 表面安装的集成电路管芯封装包括从封装的周边横向向外延伸的一组外围引线，并且还包括在封装的底部上的焊球阵列。 该布置通过利用外围引线和球栅阵列来提供更大数量的对封装的输入/输出连接，而不需要增加封装尺寸或减小导电互连的宽度。

公开(公告)号：US5745986A

公开(公告)日：1998-05-05

申请号：US506382

申请日：1995-07-24

Applicant: Patrick Variot ,  Chok J. Chia ,  Robert T. Trabucco

Inventor： Patrick Variot ,  Chok J. Chia ,  Robert T. Trabucco

IPC: H01L21/00 ,  H01L21/48 ,  H05K3/34 ,  H05K13/04

CPC classification number: H01L21/67092 ,  H01L21/4853 ,  H05K3/3436 ,  H05K3/3457 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1403 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/75743 ,  H01L2924/3511 ,  H05K2201/094 ,  H05K2201/10734 ,  H05K2203/0278 ,  H05K3/3431 ,  Y02P70/613 ,  Y10S29/044 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/53191

Abstract: A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit on a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.

Abstract translation: 一种用于安装集成电路的方法包括排列在电路板上的集成电路的封装的底表面上的多个焊球。 这些焊球通过焊料回流提供集成电路到电路板的表面安装。 焊球的阵列可以被平坦化，使得多个焊球中的每一个参与限定用于集成电路封装的真正平坦的焊球接触阵列。 阐述了制造集成电路的方法，该封装具有依赖于其底表面的阵列中的平坦化焊球。 集成电路封装的真正平面化的焊球接触阵列在集成电路封装和封装要安装的电路板之间形成表面安装电连接几乎绝对可靠。

公开(公告)号：US5435482A

公开(公告)日：1995-07-25

申请号：US192081

申请日：1994-02-04

Applicant: Patrick Variot ,  Chok J. Chia ,  Robert T. Trabucco

Inventor： Patrick Variot ,  Chok J. Chia ,  Robert T. Trabucco

IPC: H01L21/00 ,  H01L21/48 ,  H05K3/34 ,  H05K13/04 ,  H01L21/603

CPC classification number: H01L21/67092 ,  H01L21/4853 ,  H05K3/3436 ,  H05K3/3457 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1403 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/75743 ,  H01L2924/3511 ,  H05K2201/094 ,  H05K2201/10734 ,  H05K2203/0278 ,  H05K3/3431 ,  Y02P70/613 ,  Y10S29/044 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/53191

Abstract: An integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount. Additionally, the planarized solder ball contacts locally compensate individually for warpage of the integrated circuit package by variation in the individual dimensions of dependency of each solder ball below the bottom surface of the package.

Abstract translation: 集成电路包括排列在集成电路的封装的底表面上的多个焊球。 这些焊球通过焊料回流提供集成电路到电路板的表面安装。 焊球的阵列可以被平坦化，使得多个焊球中的每一个参与限定用于集成电路封装的真正平坦的焊球接触阵列。 阐述了制造集成电路的方法，该封装具有依赖于其底表面的阵列中的平坦化焊球。 集成电路封装的真正平面化的焊球接触阵列在集成电路封装和封装要安装的电路板之间形成表面安装电连接几乎绝对可靠。 此外，平坦化的焊球接触器通过在封装的底表面下方的每个焊球的依赖性的各个维度的变化来单独地局部补偿集成电路封装的翘曲。

公开(公告)号：US5981311A

公开(公告)日：1999-11-09

申请号：US104838

申请日：1998-06-25

Applicant: Chok J. Chia ,  Seng Sooi Lim ,  Patrick Variot

Inventor： Chok J. Chia ,  Seng Sooi Lim ,  Patrick Variot

IPC: H01L21/48 ,  H05K3/24 ,  H05K3/42 ,  H01L21/58 ,  H01L21/28 ,  H01L21/304

CPC classification number: H05K3/242 ,  H01L21/4846 ,  H05K3/428 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K2203/0191 ,  H05K2203/0361 ,  H05K2203/1572

Abstract: A method of electroplating a high density integrated circuit (IC) substrate using a removable plating bus including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces formed on its surface. Attaching a removable plating bus to the IC substrate, covering the plurality of conductive traces. Forming through holes (or vias) in predetermined locations. The holes going through the removable plating bus and IC substrate, exposing edges of selected conductive traces in the holes. Plating the through holes with a conductive material (such as copper) that electrically connects the removable plating bus to the exposed edges of the traces in the holes. Coating the IC substrate (including the removable plating bus) with plating resist and selectively removing portions of the removable plating bus, along with the plating resist, to expose selected areas of traces on the IC substrate that require plating. Electroplating the exposed trace areas on the IC substrate with conductive material (such as gold or nickel) by using the removable plating bus as the electrical connection to the exposed metal traces and removing the removable plating bus after electroplating is finished.

Abstract translation: 一种使用可移除电镀母线电镀高密度集成电路（IC）衬底的方法，包括以下步骤：提供由其表面上形成有多个导电迹线的非导电材料制成的IC衬底。 将可移除的电镀母线安装到IC基板上，覆盖多个导电迹线。 在预定位置形成通孔（或通孔）。 穿过可移除电镀总线和IC基板的孔，暴露孔中选定导电迹线的边缘。 用诸如铜的导电材料（例如铜）电镀通孔，其将可移除的电镀总线电连接到孔中的迹线的暴露边缘。 用电镀抗蚀剂涂覆IC基板（包括可移除电镀总线），并与电镀抗蚀剂一起选择性地去除可移除电镀母线的部分，以暴露需要电镀的IC基板上的选定区域的痕迹。 通过使用可移除的电镀母线作为与暴露的金属迹线的电气连接，并且在电镀完成之后移除可移除的电镀母线，用导电材料（例如金或镍）电镀IC衬底上的暴露痕迹区域。

公开(公告)号：US5901437A

公开(公告)日：1999-05-11

申请号：US960831

申请日：1997-10-30

Applicant: Patrick Variot ,  Chok J. Chia ,  Robert T. Trabucco

Inventor： Patrick Variot ,  Chok J. Chia ,  Robert T. Trabucco

IPC: H01L21/00 ,  H01L21/48 ,  H05K3/34 ,  H05K13/04

CPC classification number: H01L21/67092 ,  H01L21/4853 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1403 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/75743 ,  H01L2924/3511 ,  H05K3/3431 ,  H05K3/3436 ,  H05K3/3457 ,  H05K2201/094 ,  H05K2201/10734 ,  H05K2203/0278 ,  Y02P70/613 ,  Y10S29/044 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/53191

Abstract: A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit onto to a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount. Additionally, the planarized solder ball contacts locally compensate individually for warpage of the integrated circuit package by variation in the individual dimensions of dependency of each solder ball below the bottom surface of the package.

公开(公告)号：US5869889A

公开(公告)日：1999-02-09

申请号：US840614

申请日：1997-04-21

Applicant: Chok J. Chia ,  Patrick Variot ,  Maniam Alagaratnam

Inventor： Chok J. Chia ,  Patrick Variot ,  Maniam Alagaratnam

IPC: H01L23/29 ,  H01L21/60 ,  H01L23/12 ,  H01L23/24 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L23/34

CPC classification number: H01L23/36 ,  H01L23/24 ,  H01L23/4985 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181

Abstract: An integrated circuit package includes a heatspreader which is formed to have a centrally disposed recessed portion between planar surfaces, and flex tape extending from the planar surfaces into the centrally disposed surface. A semiconductor chip is mounted on the centrally disposed surface between the flex tape, and wire bonds interconnect bonding pads on the chip to the metal interconnect patterns on the flex tape. Plastic molding or epoxy is then applied to encapsulate the chip and wire bonding in the centrally disposed planar surface of the heat spreader. The package is then readily mounted on a motherboard using solder balls.

Abstract translation: 集成电路封装包括散热器，其形成为在平面之间具有居中设置的凹部，以及从平面延伸到中心设置表面的柔性带。 半导体芯片安装在柔性带之间的中央布置的表面上，并且引线将芯片上的接合焊盘互连到柔性带上的金属互连图案。 然后施加塑料模制或环氧树脂以将芯片和引线接合封装在散热器的中心设置的平坦表面中。 然后使用焊球将封装容易地安装在母板上。

公开(公告)号：US5789811A

公开(公告)日：1998-08-04

申请号：US725735

申请日：1996-10-04

Applicant: Chok J. Chia ,  Patrick Variot

Inventor： Chok J. Chia ,  Patrick Variot

IPC: H01L23/12 ,  H01L23/24 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H05K3/34 ,  H01L23/02

CPC classification number: H01L23/24 ,  H01L23/3128 ,  H01L23/49531 ,  H01L23/49811 ,  H01L23/49816 ,  H05K3/341 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H05K2201/10659 ,  H05K2201/10681 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/613

Abstract: A surface mounted integrated circuit die package includes a group of peripheral leads extending laterally outwardly from the perimeter of the package and also includes an array of solder balls on the bottom of the package. The arrangement provides for a greater number of input/output connections to a die package by utilizing both peripheral leads and a ball grid array without requiring increases in package size or a reduction in the width of electrically conductive interconnections.

公开(公告)号：US5557150A

公开(公告)日：1996-09-17

申请号：US429605

申请日：1995-04-27

Applicant: Patrick Variot ,  Chok J. Chia

Inventor： Patrick Variot ,  Chok J. Chia

IPC: G03F7/20 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/544 ,  H01L29/06 ,  H01L23/28

CPC classification number: G03F7/70433 ,  H01L23/3121 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/544 ,  H01L2223/54473 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/49 ,  H01L29/0657 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15162 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18301

Abstract: A technique for providing partially and fully overmolded semiconductor packages is described which prevents delamination (detachment) of the molding compound from the substrate by allowing the molding compound to flow through holes in the substrate and forming it into rivet-like anchors on the opposite side of the substrate. Various shapes of rivet-like anchors are described. Different embodiments provide for the formation of molded standoffs and locating pins integral to the anchor structures.

Abstract translation: 描述了一种用于提供部分和完全包覆模制的半导体封装的技术，其通过允许模塑料流过衬底中的孔并将其形成铆钉状锚固体，从而防止模塑料从衬底的分层（脱离） 底物。 描述了各种形状的铆钉状锚固件。 不同的实施例提供模制支座的形成和与锚结构一体的定位销。