公开(公告)号：US07223652B2

公开(公告)日：2007-05-29

申请号：US11048556

申请日：2005-02-01

Applicant: Kiyoshi Ooi ,  Yasuyoshi Horikawa ,  Tomoo Yamasaki

Inventor： Kiyoshi Ooi ,  Yasuyoshi Horikawa ,  Tomoo Yamasaki

IPC: H01L21/338 ,  H01L51/40 ,  H01L21/8244 ,  H01L21/8242

CPC classification number: H01G4/224 ,  H01L21/6835 ,  H01L23/50 ,  H01L23/642 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/162 ,  H05K2201/0162 ,  H05K2201/09763 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2224/05166

Abstract: A capacitor includes a capacitor part formed of a dielectric film sandwiched by a pair of electrodes and a support body formed of a film of an organic polysilane. The support body is provided so as to support the capacitor part thereon.

Abstract translation: 电容器包括由夹在一对电极之间的电介质膜和由有机聚硅烷膜形成的支撑体形成的电容器部分。 支撑体设置成在其上支撑电容器部分。

公开(公告)号：US20070102811A1

公开(公告)日：2007-05-10

申请号：US11523270

申请日：2006-09-19

Applicant: Madhavan Swaminathan ,  Ege Engin ,  Prathap Muthana ,  Krishna Srinivasan

Inventor： Madhavan Swaminathan ,  Ege Engin ,  Prathap Muthana ,  Krishna Srinivasan

IPC: H01L23/04

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/3011 ,  H05K1/162 ,  H05K2201/09763 ,  H05K2201/10674 ,  Y10S257/924

Abstract: One embodiment of the present invention provides advice for providing a low noise power supply package to an integrated circuit comprising a semiconductor die, input/output power supply terminals, and an array of embedded ceramic capacitors selected from discrete, planar and combinations thereof wherein said capacitors are placed in the locations selected from within the perimeter of the shadow of the semiconductor die, partially within the perimeter of the shadow of the semiconductor die, near the perimeter of the shadow of the semiconductor die, and combinations thereof.

Abstract translation: 本发明的一个实施例提供了向包括半导体管芯，输入/输出电源端子以及选自离散，平面和组合的嵌入式陶瓷电容器阵列的集成电路提供低噪声电源封装的建议，其中所述电容器 被放置在从半导体管芯的阴影的周边中选择的位置，部分地在半导体管芯的阴影的周边内，靠近半导体管芯的阴影的周边，以及它们的组合。

公开(公告)号：US20060289976A1

公开(公告)日：2006-12-28

申请号：US11166962

申请日：2005-06-23

Applicant: Yongki Min

Inventor： Yongki Min

IPC: H01L23/02

CPC classification number: H01L23/49822 ,  H01G4/228 ,  H01G4/33 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12044 ,  H01L2924/15311 ,  H05K1/162 ,  H05K3/048 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09763 ,  H01L2924/00

Abstract: An embedded passive structure, its method of formation, and its intergration onto a substrate during fabrication are disclosed, In one embodiment the embedded passive structure is a thin film capacitor (TFC) formed using a thin film laminate that has been mounted onto a substrate. The TFC's capacitor dielectric and/or lower electrode layers are patterned in such a way as to reduce damage and improve cycle time. In one embodiment, the capacitor dielectric has a high dielectric constant and the substrate is an organic packaging substrate.

Abstract translation: 公开了嵌入式无源结构，其形成方法及其在制造过程中与衬底的集成。在一个实施例中，嵌入式无源结构是使用已经安装到衬底上的薄膜层压体形成的薄膜电容器（TFC）。 TFC的电容器电介质和/或下电极层被图案化以减少损坏并改善循环时间。 在一个实施例中，电容器电介质具有高介电常数，并且衬底是有机封装衬底。

公开(公告)号：US20060284280A1

公开(公告)日：2006-12-21

申请号：US11453496

申请日：2006-06-15

Applicant: William Borland ,  Saul Ferguson ,  Diptarka Majumdar ,  Richard Traylor

Inventor： William Borland ,  Saul Ferguson ,  Diptarka Majumdar ,  Richard Traylor

IPC: H01L29/00 ,  H01L21/00

CPC classification number: H01L21/20 ,  H05K1/092 ,  H05K1/162 ,  H05K3/1291 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126

Abstract: A method of embedding thick-film fired-on-foil capacitors includes entirely covering the dielectric with an encapsulating electrode to avoid cracking in the dielectric due to shrinkage and temperature coefficient of expansion differences between the electrode and dielectric.

Abstract translation: 包埋厚膜烧结箔电容器的方法包括用封装电极完全覆盖电介质，以避免由于电极和电介质之间的收缩和温度膨胀系数差导致电介质中的开裂。

公开(公告)号：US20060281278A1

公开(公告)日：2006-12-14

申请号：US11152328

申请日：2005-06-14

Applicant: Yongki Min

Inventor： Yongki Min

IPC: H01L21/20 ,  H01L21/44

CPC classification number: H01L27/016 ,  H01L21/4857 ,  H01L23/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/16152 ,  H05K1/162 ,  H05K3/025 ,  H05K3/4652 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2203/0384 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A thin-film capacitor assembly includes a first metal bottom electrode, a dielectric layer, a second metal etch-stop layer, and a subsequent metal top electrode. The first metal bottom electrode is in contact with the dielectric layer. The second metal etch-stop layer is in contact with the dielectric layer. The subsequent metal top electrode is in contact with the second metal etch-stop layer. Processing of the thin-film capacitor assembly includes totally removing a stiffener after assembling the first metal bottom electrode as a layer to the dielectric layer and the second metal etch-stop layer. The stiffener is removed from above and on the second metal etch-stop layer. The thin-film capacitor assembly is laminated to a mounting substrate.

公开(公告)号：US20060262481A1

公开(公告)日：2006-11-23

申请号：US11436697

申请日：2006-05-18

Applicant: Yasuaki Mashiko

Inventor： Yasuaki Mashiko

IPC: H01G4/228 ,  H01G4/10 ,  H01G4/06

CPC classification number: H05K1/162 ,  H01G4/228 ,  H01G4/33 ,  H01L27/016 ,  H05K1/0393 ,  H05K3/243 ,  H05K3/3457 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09763 ,  H05K2201/10681

Abstract: The present invention provides a manufacturing method capable of mass production of a thin film decoupling capacitor provided with a capacitor circuit on the surface of a film tape carrier form of a polyimide resin or the like. For the purpose of achieving the above described object, there is provided a film carrier tape with a capacitor circuit, including a wiring pattern on the surface of a resin film including a plurality of sprocket holes on each of the two edges, wherein the resin film includes solder ball land holes and the wiring pattern includes a capacitor circuit having a structure in which a dielectric layer is disposed between an upper electrode and a lower electrode. As the method for manufacturing the aforementioned film carrier tape, there is provided such a method for semicontinuously manufacturing the film carrier tape concerned in the state of tape as applied to manufacturing conventional TAB products.

Abstract translation: 本发明提供一种能够大量生产在聚酰亚胺树脂等的薄膜带载体的表面上设置有电容器电路的薄膜去耦电容器的制造方法。 为了实现上述目的，提供了一种具有电容器电路的薄膜载带，其包括在包括两个边缘中的每一个上的多个链轮孔的树脂膜的表面上的布线图案，其中树脂膜 包括焊球接地孔，并且布线图案包括电容器电路，其电介质层设置在上电极和下电极之间。 作为制造上述薄膜载带的方法，提供了一种在制造传统的TAB产品时，以带状状半连续制造薄膜载带的方法。

公开(公告)号：US20060254812A1

公开(公告)日：2006-11-16

申请号：US11486505

申请日：2006-07-14

Applicant: William Borland ,  Saul Ferguson ,  Hena Pyada

Inventor： William Borland ,  Saul Ferguson ,  Hena Pyada

IPC: H05K1/16 ,  H01G7/00

CPC classification number: H05K1/162 ,  H05K3/061 ,  H05K3/429 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  Y10T29/43 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of forming printed wiring boards having embedded thick-film capacitors includes covering capacitor layers with a protective coating prior to etching to prevent etching solutions from contacting with and damaging the capacitor layers and forming vias directly between the capacitor electrodes and the board circuitry.

Abstract translation: 形成具有嵌入式厚膜电容器的印刷电路板的方法包括在蚀刻之前用保护涂层覆盖电容器层，以防止蚀刻溶液与电容器层接触并损坏电容器层，并直接在电容器电极和电路板电路之间形成通孔。

公开(公告)号：US20060254050A1

公开(公告)日：2006-11-16

申请号：US11489544

申请日：2006-07-20

Applicant: Yoshitaka Fukuoka ,  Tooru Serizawa ,  Hiroshi Yagi ,  Osamu Shimada ,  Hiroyuki Hirai ,  Yuji Yamaguchi

Inventor： Yoshitaka Fukuoka ,  Tooru Serizawa ,  Hiroshi Yagi ,  Osamu Shimada ,  Hiroyuki Hirai ,  Yuji Yamaguchi

IPC: C09D5/00 ,  B05D3/12

CPC classification number: H05K1/162 ,  H05K1/095 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09763 ,  H05K2203/0338 ,  H05K2203/1189 ,  Y10T29/4902 ,  Y10T29/49099 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: A fabricating method of a wiring board provided with passive elements is disclosed. The fabricating method includes coating one or both of resistive paste and dielectric paste on at least any one of first surfaces of a first metal foil and a second metal foil each of which has a first surface and a second surface; arranging an insulating board having thermo-plasticity and thermo-setting properties so as to face the first surface of the first metal foil, and arranging the first surface side of the second metal foil so as to face a surface different from a surface to which the first metal foil faces of the insulating board; forming a double-sided wiring board by stacking, pressurizing and heating the arranged first metal foil, insulating board, and second metal foil, and thereby integrating these; and patterning the first metal foil and/or the second metal foil.

Abstract translation: 公开了一种具有无源元件的布线板的制造方法。 制造方法包括在第一金属箔和第二金属箔的至少一个第一表面上涂覆电阻浆料和电介质浆料中的一种或两种，每个第一表面具有第一表面和第二表面; 布置具有热塑性和热固性的绝缘板，以便面对第一金属箔的第一表面，并且将第二金属箔的第一表面侧布置成面对不同于表面的表面 绝缘板的第一金属箔面; 通过对所配置的第一金属箔，绝缘板和第二金属箔进行堆叠，加压和加热来形成双面布线板，从而将它们集成; 以及图案化第一金属箔和/或第二金属箔。

公开(公告)号：US07091589B2

公开(公告)日：2006-08-15

申请号：US10497536

申请日：2003-12-10

Applicant: Toshiaki Mori ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

Inventor： Toshiaki Mori ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

IPC: H01L23/02

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/0366 ,  H05K1/162 ,  H05K3/0041 ,  H05K3/0044 ,  H05K3/388 ,  H05K3/4061 ,  H05K3/4069 ,  H05K3/4076 ,  H05K3/426 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/09763 ,  H05K2201/09827 ,  H05K2203/025 ,  H05K2203/1338 ,  H05K2203/1581 ,  Y10T29/43 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.

Abstract translation: 在层叠在所述芯板的一个表面上的芯板，布线层和电绝缘层的多层布线基板中，所述芯板的XY方向的热膨胀系数在2〜20ppm的范围内 所述芯板的核心部件是选自硅，陶瓷，玻璃，玻璃 - 环氧复合材料和金属的核心部件，所述芯板设置有多个在正面和背面之间导电的通孔 通过导电材料，并且在所述芯板的一个表面上设置电容器，其中所述电容器包括在所述通孔中作为导电材料的上电极和设置成经由电介质层面对所述上电极的下电极 。

公开(公告)号：US20060176350A1

公开(公告)日：2006-08-10

申请号：US11331186

申请日：2006-01-13

Applicant: James Howarth ,  Chuck Edwards ,  Karel Vanheusden

Inventor： James Howarth ,  Chuck Edwards ,  Karel Vanheusden

IPC: B41J2/01

CPC classification number: B41J2/01 ,  B41J2202/04 ,  H01C17/065 ,  H05K1/095 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/181 ,  H05K3/125 ,  H05K2201/09763 ,  H05K2203/013 ,  H05K2203/1453

Abstract: A process of fabricating a passive electrical component, such as a resistor, a capacitor, or an inductor, is provided. The process includes the step of ink-jet printing at least one electronic ink onto a substrate in a predetermined pattern. The step of ink-jet printing may include the steps of: a) selecting at least one electronic ink having at least one electrical characteristic when cured; b) determining a positional layout for a plurality of droplets of the at least one electronic ink such that, when the at least one electronic ink has been cured, the positional layout provides a desired response for the electrical component; c) printing each of the plurality of droplets of the at least one electronic ink onto the substrate according to the positional layout using an ink-jet printing process; and d) curing the at least one electronic ink.

Abstract translation: 提供了制造无源电部件的工艺，例如电阻器，电容器或电感器。 该方法包括以预定图案将至少一种电子墨水喷墨印刷到基底上的步骤。 喷墨印刷的步骤可以包括以下步骤：a）选择至少一种在固化时具有至少一种电特性的电子墨水; b）确定所述至少一个电子墨水的多个液滴的位置布局，使得当所述至少一个电子墨水已经固化时，所述位置布局为所述电气部件提供期望的响应; c）使用喷墨打印方法根据所述位置布局将所述至少一个电子墨水的所述多个液滴中的每一个印刷到所述基板上; 以及d）固化所述至少一个电子墨水。