公开(公告)号：US09263537B2

公开(公告)日：2016-02-16

申请号：US14526126

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

IPC: H01L21/70 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/42364 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

Abstract translation: 本文公开的一种方法包括形成封装并保护栅极盖层的第一和第二栅极盖保护层。 本文公开的新型晶体管器件包括位于半导体衬底上方的栅极结构，邻近栅极结构定位的间隔结构，位于衬底上方并围绕间隔结构的绝缘材料层，位于栅极结构之上的栅极盖层， 所述间隔结构以及封装所述栅极盖层的栅极帽保护材料，其中所述栅极盖保护材料的部分位于所述栅极盖层和所述栅极结构之间，所述间隔物结构和所述绝缘材料层。

公开(公告)号：US20160005733A1

公开(公告)日：2016-01-07

申请号：US14855881

申请日：2015-09-16

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Michael Wedlake ,  Xiuyu Cai ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/28017 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7833

Abstract: One illustrative device disclosed includes, among other things, first and second active regions that are separated by an isolation region, first and second replacement gate structures positioned above the first and second active regions, respectively, and a gate registration structure positioned above the isolation region, wherein the gate registration structure comprises a layer of insulating material positioned above the isolation region and a polish-stop layer and wherein a first end surface of the first replacement gate structure abuts and engages a first side surface of the gate registration structure and a second end surface of the second replacement gate structure abuts and engages a second side surface of the gate registration structure.

Abstract translation: 所公开的一个说明性装置尤其包括被隔离区隔开的第一和第二有源区，分别位于第一和第二有源区上方的第一和第二置换栅极结构以及位于隔离区上方的栅极配准结构 ，其中所述栅极配准结构包括位于所述隔离区域上方的绝缘材料层和抛光停止层，并且其中所述第一替换栅极结构的第一端表面邻接并接合所述栅极配准结构的第一侧表面， 第二替换栅极结构的端面邻接并接合栅极配准结构的第二侧表面。

公开(公告)号：US09231051B2

公开(公告)日：2016-01-05

申请号：US14579428

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  William J. Taylor, Jr.

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/02263 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure.

公开(公告)号：US20150372108A1

公开(公告)日：2015-12-24

申请号：US14309096

申请日：2014-06-19

Applicant: GlobalFoundries Inc.

Inventor： Xiuyu Cai ,  Ying Hao Hsieh

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/51 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/6656 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.

Abstract translation: 本发明的实施例提供了用于在外延生长期间保护栅极的方法和结构。 第一材料的内部间隔物沉积在晶体管栅极附近。 不同材料的外部间隔物邻近内部间隔物沉积。 在晶体管栅极附近形成应力腔。 内部间隔件凹入，形成一个凹槽。 该divot充满了材料，以保护晶体管门。 然后填充压力腔。 当门被安全地保护时，防止晶体管栅极上的不期望的外延生长（“鼠标耳”）。

公开(公告)号：US20150371892A1

公开(公告)日：2015-12-24

申请号：US14307902

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/308 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L21/76224 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/1029 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853

Abstract: One method disclosed includes, among other things, forming an overall fin structure having a stepped cross-sectional profile, the fin structure having an upper part and a lower part positioned under the upper part, wherein the upper part has a first width and the lower part has a second width that is less than the first width, forming a layer of insulating material in trenches adjacent the overall fin structure such that the upper part of the overall fin structure and a portion of the lower part of the overall fin structure are exposed above an upper surface of the layer of insulating material, and forming a gate structure around the exposed upper part of the overall fin structure and the exposed portion of the lower part of the overall fin structure.

Abstract translation: 所公开的一种方法包括形成具有阶梯状横截面轮廓的整体翅片结构，翅片结构具有位于上部下方的上部和下部，其中上部具有第一宽度和下部 部分具有小于第一宽度的第二宽度，在邻近整个翅片结构的沟槽中形成绝缘材料层，使得整个翅片结构的上部和整个翅片结构的下部的一部分暴露 在绝缘材料层的上表面之上，并且围绕整个翅片结构的暴露的上部和整个翅片结构的下部的暴露部分形成栅极结构。

公开(公告)号：US09190487B2

公开(公告)日：2015-11-17

申请号：US14283409

申请日：2014-05-21

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

公开(公告)号：US09184263B2

公开(公告)日：2015-11-10

申请号：US14143468

申请日：2013-12-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Daniel T. Pham ,  Mark V. Raymond ,  Christopher M. Prindle ,  Catherine B. Labelle ,  Linus Jang ,  Robert Teagle

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/417 ,  H01L29/51 ,  H01L29/423 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/31055 ,  H01L21/76897 ,  H01L29/0692 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.

Abstract translation: 本文公开的一种方法尤其包括邻近牺牲栅极结构的牺牲栅电极的相对侧的侧壁间隔壁，形成邻近侧壁间隔物的绝缘材料的拉应力层，去除牺牲栅极结构以限定替换 门腔定位在侧壁间隔件之间，在置换栅腔中形成替换栅极结构，在置换栅极结构之上和置换栅极腔内形成拉伸应力栅极盖层，并且在形成拉伸应力栅极盖层之后， 去除绝缘材料的拉应力层。

公开(公告)号：US20150279742A1

公开(公告)日：2015-10-01

申请号：US14242046

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Michael Wedlake ,  Xiuyu Cai ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L21/8234 ,  H01L21/321 ,  H01L21/28 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/28017 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7833

Abstract: One method disclosed includes, among other things, forming a gate registration structure above an isolation region, wherein the gate registration structure comprises a plurality of layers of material, the uppermost layer of which is a polish-stop layer, forming first and second sacrificial gate structures above first and second active regions, respectively, wherein the first and second sacrificial gate structures abut and engage opposite sides of the gate registration structure, and performing at least one first chemical mechanical polishing (CMP) process to remove the gate cap layer so as to thereby expose a sacrificial gate electrode in each of the first and second sacrificial gate structures, wherein the uppermost layer of the gate registration structure serves as a polish-stop layer during the at least one first CMP process.

Abstract translation: 公开的一种方法包括在隔离区域之上形成栅极配准结构，其中栅极配准结构包括多层材料，其最上层是抛光停止层，形成第一和第二牺牲栅极 分别在第一和第二有源区域之上的结构，其中第一和第二牺牲栅极结构邻接并接合栅极对准结构的相对侧，并且执行至少一个第一化学机械抛光（CMP）工艺以移除栅极盖层，以便 从而在第一和第二牺牲栅极结构中的每一个中露出牺牲栅电极，其中栅极配准结构的最上层在至少一个第一CMP工艺期间用作抛光停止层。

公开(公告)号：US09142651B1

公开(公告)日：2015-09-22

申请号：US14226488

申请日：2014-03-26

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/336 ,  H01L29/76 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/66537 ,  H01L21/2236 ,  H01L21/324 ,  H01L27/0886 ,  H01L29/1083 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/785

Abstract: One method disclosed includes, among other things, covering a top surface and a portion of the sidewalls of a fin with etch stop material, forming a sacrificial gate structure above and around the fin, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one process operation to remove the sacrificial gate structure and thereby define a replacement gate cavity, forming a counter-doped region in the fin below an upper surface of the fin and below the channel region of the device, wherein the counter-doped region is doped with a second type of dopant material that is of an opposite type relative to the first type of dopant material, and forming a replacement gate structure in the replacement gate cavity.

Abstract translation: 公开的一种方法包括用蚀刻停止材料覆盖翅片的顶表面和一部分侧壁，在翅片上方和周围形成牺牲栅极结构，形成邻近牺牲栅极结构的侧壁间隔件， 至少一个处理操作以去除所述牺牲栅极结构，从而限定替换栅极腔，在所述鳍片的下表面以下且在所述器件的沟道区域下方形成鳍片中的反掺杂区域，其中所述反掺杂区域为 掺杂有相对于第一种掺杂剂材料相反类型的第二类型的掺杂剂材料，以及在替换栅极腔中形成替代栅极结构。

公开(公告)号：US20150255608A1

公开(公告)日：2015-09-10

申请号：US14200952

申请日：2014-03-07

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, forming an initial fin structure comprised of portions of a substrate, a first epi semiconductor material and a second epi semiconductor material, forming a layer of insulating material so as to over-fill the trenches that define the fin, recessing a layer of insulating material such that a portion, but not all, of the second epi semiconductor portion of the final fin structure is exposed, forming a gate structure around the final fin structure, further recessing the layer of insulating material such that the first epi semiconductor material is exposed, removing the first epi semiconductor material to thereby define an under-fin cavity and substantially filling the under-fin cavity with a stressed material.

Abstract translation: 所公开的一种方法包括形成由衬底，第一外延半导体材料和第二外延半导体材料的部分组成的初始鳍结构，形成绝缘材料层，从而过度填充限定 翅片，使一层绝缘材料凹陷，使得最终翅片结构的第二外延半导体部分的一部分（但不是全部）暴露，围绕最终翅片结构形成栅极结构，进一步使绝缘材料层凹陷，使得 第一外延半导体材料被暴露，去除第一外延半导体材料，从而限定下鳍腔，并用受压材料基本上填充底鳍腔。