公开(公告)号：US20060050489A1

公开(公告)日：2006-03-09

申请号：US11255061

申请日：2005-10-19

Applicant: James Wehrly ,  Mark Wolfe ,  Paul Goodwin

Inventor： James Wehrly ,  Mark Wolfe ,  Paul Goodwin

IPC: H05K1/00

CPC classification number: H05K1/189 ,  H01L25/0652 ,  H01L25/105 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K1/118 ,  H05K1/181 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of its major sides. Contacts are distributed along the flexible circuitry to provide connection between the module and an application environment. A rigid substrate is configured to provide space on one side where the populated flex is disposed while in some embodiments, heat management or cooling structures are arranged on one side of the module to mitigate thermal accumulation in the module.

公开(公告)号：US20060049513A1

公开(公告)日：2006-03-09

申请号：US11193954

申请日：2005-07-29

Applicant: Paul Goodwin

Inventor： Paul Goodwin

IPC: H01L23/34

CPC classification number: G11C5/00 ,  G11C5/143 ,  H01L23/34 ,  H01L23/36 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/118 ,  H05K1/181 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2203/1572 ,  H01L2224/0401

Abstract: A flex circuit populated with integrated circuits on one or both sides and in one or more fields along the flex circuitry is wrapped about an edge of a supporting substrate. In preferred embodiments, the substrate is thermally conductive material. One side of the flex circuitry has a connective facility implemented in a preferred embodiment with edge connector contacts such as those that would allow the resulting module to be inserted into an expansion socket. In a preferred embodiment, integrated circuits (preferably memory CSPs) and any accompanying circuitry or buffers are arranged on one or both sides of a flexible circuit. In some embodiments, one or more thermal sensors or other indicators are thermally coupled to the module substrate.

Abstract translation: 在柔性电路的一侧或两侧以及一个或多个场中填充有集成电路的柔性电路围绕支撑衬底的边缘缠绕。 在优选实施例中，基底是导热材料。 柔性电路的一侧具有在优选实施例中实现的连接设备，其中边缘连接器触点例如将允许所得到的模块插入到扩展插座中的连接器触点。 在优选实施例中，集成电路（优选存储器CSP）和任何伴随的电路或缓冲器布置在柔性电路的一侧或两侧。 在一些实施例中，一个或多个热传感器或其它指示器热耦合到模块基板。

公开(公告)号：US20050285264A1

公开(公告)日：2005-12-29

申请号：US10877256

申请日：2004-06-28

Applicant: William Burdick ,  James Rose ,  Michael Rumsey

Inventor： William Burdick ,  James Rose ,  Michael Rumsey

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01R12/00 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01R12/62 ,  H01L23/4985 ,  H01L23/5387 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/118 ,  H05K1/189 ,  H05K2201/056 ,  H05K2201/10719 ,  H01L2924/00

Abstract: A high density electrical interconnecting system of the present invention has at least one substrate piece and a flexible wrap-around interconnect assembly extending from a first surface of the substrate piece to a second surface of the substrate piece wherein the flexible wrap-around interconnect is disposed around an outer surface of the substrate piece.

Abstract translation: 本发明的高密度电互连系统具有至少一个基片和柔性环绕互连组件，该基片和柔性环绕互连组件从基片的第一表面延伸到基片的第二表面，其中布置柔性环绕互连 围绕基片的外表面。

公开(公告)号：US20050284657A1

公开(公告)日：2005-12-29

申请号：US11199484

申请日：2005-08-08

Applicant: Chang-Sup Ryu ,  Jang-Kyu Kang ,  Byung-Kook Sun

Inventor： Chang-Sup Ryu ,  Jang-Kyu Kang ,  Byung-Kook Sun

IPC: H05K1/14 ,  H05K1/11 ,  H05K3/28 ,  H05K3/40 ,  H01R12/04

CPC classification number: H05K3/403 ,  H05K1/118 ,  H05K3/28 ,  H05K2201/055 ,  H05K2201/056 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: Disclosed is a method of fabricating a double-sided PCB without via holes, functioning to transport electric signals between both sides of the PCB, by folding a flexible substrate, in which circuit patterns are formed on only one side of the flexible substrate, and the double-sided PCB without the via holes fabricated by the method. Therefore, the method is advantageous in that it allows PCB manufacturers to save the efforts for forming and protecting the via holes because the double-sided PCB does not need via holes, and reduces its fabricating cost and time, due to simplicity of this method.

Abstract translation: 公开了一种制造无通孔的双面PCB的方法，其功能是在PCB的两侧之间传输电信号，通过折叠柔性基板，其中电路图案仅形成在柔性基板的一侧上，并且 双面PCB，无通孔的方法。 因此，该方法的优点在于，由于双面PCB不需要通孔，所以PCB制造商可以节省形成和保护通孔的努力，并且由于该方法的简单性而降低了其制造成本和时间。

公开(公告)号：US20050167803A1

公开(公告)日：2005-08-04

申请号：US11043946

申请日：2005-01-28

Applicant: Hiroyuki Imamura

Inventor： Hiroyuki Imamura

IPC: H01L21/60 ,  G02F1/13 ,  G02F1/1345 ,  H01L23/34 ,  H01L23/498 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/10 ,  H05K3/24 ,  H05K3/36

CPC classification number: H05K1/189 ,  G02F1/13452 ,  H01L23/4985 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/19043 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0281 ,  H05K1/111 ,  H05K1/117 ,  H05K3/0097 ,  H05K3/108 ,  H05K3/243 ,  H05K3/361 ,  H05K2201/056 ,  H05K2201/09063 ,  H05K2201/09736 ,  H05K2201/09781 ,  H05K2201/10128 ,  H05K2201/10674 ,  H05K2201/10681 ,  H05K2201/2009 ,  H05K2203/0574 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/05599

Abstract: In a film substrate (FB) including a film base material (1) and conductor wiring (23) that is formed on the film base material (1), the conductor wiring (23) is arranged such that the conductor wiring thickness of an external connection portion on the film substrate to which another panel or substrate is connected is thicker than the conductor wiring thickness of conductor wiring portions (bent portions) (25) at other positions.

Abstract translation: 在薄膜基材（1）和形成在薄膜基材（1）上的导体布线（23）的薄膜基板（FB）中，导体布线（23）布置成使外部的导体布线厚度 连接另一面板或基板的薄膜基板上的连接部分比其他位置的导体布线部分（弯曲部分）（25）的导体布线厚度厚。

公开(公告)号：US20050067683A1

公开(公告)日：2005-03-31

申请号：US10978149

申请日：2004-10-29

Applicant: Russell Rapport ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Jeff Buchle

Inventor： Russell Rapport ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Jeff Buchle

IPC: H01L21/44 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.

公开(公告)号：US20050062123A1

公开(公告)日：2005-03-24

申请号：US10817583

申请日：2004-04-02

Applicant: Martin Weigert

Inventor： Martin Weigert

IPC: G02B6/42 ,  H01L33/00 ,  H05K1/14 ,  H05K1/18

CPC classification number: G02B6/4202 ,  G02B6/4292 ,  H05K1/147 ,  H05K1/189 ,  H05K2201/056 ,  H05K2201/10121

Abstract: An arrangement for connecting the terminal contacts of an optoelectronic component to electrical contacts of a printed circuit board using a flexible conductor arrangement. The flexible conductor arrangement has a planar form and includes a plurality of interconnects that are arranged to provide an electrical connection between the terminal contacts of the optoelectronic component and the electrical contacts of the printed circuit board. The flexible conductor arrangement is bent in such a way that, starting from the printed circuit board, it is led around the optoelectronic component and contacts the latter on a side facing away from the printed circuit board.

Abstract translation: 一种用于使用柔性导体装置将光电子部件的端子触点与印刷电路板的电触点相连接的装置。 柔性导体装置具有平面形式并且包括多个互连件，其布置成在光电部件的端子触点和印刷电路板的电触点之间提供电连接。 柔性导体布置以这样的方式弯曲，即从印刷电路板开始，它被引导到光电子部件周围，并且在背离印刷电路板的一侧与其接触。

公开(公告)号：US20050041404A1

公开(公告)日：2005-02-24

申请号：US10958934

申请日：2004-10-05

Applicant: James Cady ,  James Wilder ,  David Roper ,  Russell Rapport ,  James Wehrly ,  Jeffrey Buchle

Inventor： James Cady ,  James Wilder ,  David Roper ,  Russell Rapport ,  James Wehrly ,  Jeffrey Buchle

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H05K1/00

CPC classification number: H01L23/49816 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00012

Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP and a support element CSP are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. The flex circuit connects the ICs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).

Abstract translation: 本发明将封装的集成电路堆叠成节省PWB或其他板表面积的模块。 本发明提供了用于将芯片级封装集成电路（CSP）或具有其他CSP的引线封装或者将单片或堆叠引线封装集成到节省PWB或其他板表面积的模块中的技术和结构。 本发明可用于各种尺寸和配置的封装，其范围从具有许多触点的较大的封装的基底元件到较小的封装，例如诸如管芯尺寸的封装（例如DSBGA）。 在根据本发明设计的优选实施例中，基体元件CSP和支撑元件CSP通过具有图案化以选择性地连接两个CSP元件的至少两个导电层的柔性电路聚集。 柔性电路连接IC，并在模块和诸如印刷电路板（PWB）的应用环境之间提供热和电连接路径。

公开(公告)号：US20040195666A1

公开(公告)日：2004-10-07

申请号：US10828495

申请日：2004-04-20

Inventor： Julian Partridge ,  James Douglas Wehrly JR.

IPC: H01L023/02

CPC classification number: H01L23/3114 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/0401

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be bonded to the flex circuitry with metallurgical bonds devised from an intermetallic that improves module stability while lowering the module profile.

Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。 在根据本发明的优选实施例中，形式标准被布置在柔性电路和IC封装之间，柔性电路的一部分放置在该IC封装上。 形式标准提供了一种物理形式，允许在采用标准连接柔性电路设计时，在广泛的CSP封装系列中发现许多变化的封装尺寸。 在一个优选实施例中，形式标准将结合到柔性电路上，其中金属间化合金设计的冶金结合能提高模块稳定性，同时降低模块轮廓。

公开(公告)号：US06770813B1

公开(公告)日：2004-08-03

申请号：US10439542

申请日：2003-05-16

Applicant: Prasanna Ramsagar ,  Andrew Z. Glovatsky

Inventor： Prasanna Ramsagar ,  Andrew Z. Glovatsky

IPC: H02G308

CPC classification number: H05K1/189 ,  B60R16/0207 ,  H05K2201/056 ,  H05K2201/10409 ,  H05K2201/2036

Abstract: A microelectronic package includes a flexible substrate and is adapted to be installed onto a support structure, which is preferably a nonplanar support structure. The package includes a frame that is affixed to a perimeter of a first portion of the flexible substrate and forms the substrate into a shape corresponding to the support structure. The package is installed so that the obverse surface of the flexible substrate is intimately against the support structure, so that the support structure not only reinforces the package to prevent damage, but also extracts heat generated during operation of the electronics.

Abstract translation: 微电子封装包括柔性基板，并且适于安装在支撑结构上，支撑结构优选为非平面支撑结构。 该包装包括固定到柔性基底的第一部分的周边并将基底形成与支撑结构对应的形状的框架。 安装包装使得柔性基底的正面紧贴支撑结构，使得支撑结构不仅加强包装以防止损坏，而且还提取在电子器件的操作期间产生的热量。