公开(公告)号：US08753913B2

公开(公告)日：2014-06-17

申请号：US13422049

申请日：2012-03-16

Applicant: Zvi Or-Bach ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Deepak C. Sekar

IPC: H01L31/18

CPC classification number: H01L27/14605 ,  H01L21/8221 ,  H01L25/0756 ,  H01L27/14612 ,  H01L27/14634 ,  H01L27/153 ,  H01L31/0725 ,  H01L31/1892 ,  H01L33/0079 ,  H01L33/34 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

Abstract: A method for fabricating an integrated device, the method including, overlying a first crystalline layer onto a second crystalline layer to form a combined layer, wherein one of the first and second crystalline layers is an image sensor layer and at least one of the first and second crystalline layers has been transferred by performing an atomic species implantation, and wherein at least one of the first and second crystalline layers includes single crystal transistors.

Abstract translation: 一种用于制造集成器件的方法，所述方法包括将第一晶体层覆盖到第二晶体层上以形成组合层，其中所述第一和第二晶体层中的一个是图像传感器层，并且所述第一和第二晶体层中的至少一个 通过进行原子物种注入已经转移了第二晶体层，并且其中第一和第二晶体层中的至少一个包括单晶晶体管。

公开(公告)号：US08669778B1

公开(公告)日：2014-03-11

申请号：US13098997

申请日：2011-05-02

Applicant: Zvi Or-Bach ,  Zeev Wurman

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F7/38 ,  G06F17/50

CPC classification number: H01L27/1128 ,  G06F17/505 ,  G06F17/5068 ,  H01L21/768 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/1305 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1778 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for the design and manufacturing of a 3D semiconductor device including a first circuit stratum and a second circuit stratum, the method including: applying a synthesis tool with at least first and second technology libraries; and performing a synthesis that utilizes the at least first and second technology libraries, where the first and second technology libraries correspond to two different processes, where the first technology library targets the first circuit stratum and the second technology library targets the second circuit stratum, and where the performing a synthesis results in a netlist, the netlist includes first cells of the first technology library and second cells of the second technology library.

Abstract translation: 一种用于设计和制造包括第一电路层和第二电路层的3D半导体器件的方法，所述方法包括：应用具有至少第一和第二技术库的合成工具; 以及执行利用所述至少第一和第二技术库的合成，其中所述第一和第二技术库对应于两个不同的过程，其中所述第一技术库针对所述第一电路层，并且所述第二技术库针对所述第二电路层，以及 在执行综合导致网表的情况下，网表包括第一技术库的第一单元和第二技术库的第二单元。

公开(公告)号：US08642416B2

公开(公告)日：2014-02-04

申请号：US13635436

申请日：2011-06-28

Applicant: Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist ,  Ze'ev Wurman

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist ,  Ze'ev Wurman

IPC: H01L21/822 ,  H01L21/8238

CPC classification number: H01L21/8221 ,  G11C16/0483 ,  G11C17/06 ,  G11C17/14 ,  G11C29/82 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/845 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/5286 ,  H01L23/535 ,  H01L23/544 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11803 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/17704 ,  H03K19/17756 ,  H03K19/17764 ,  H03K19/17796 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for formation of a semiconductor device including a first wafer including a first single crystal layer comprising first transistors and first alignment mark, the method including: implanting to form a doped layer within a second wafer; forming a second mono-crystalline layer on top of the first wafer by transferring at least a portion of the doped layer using layer transfer step, and completing the formation of second transistors on the second mono-crystalline layer including a step of forming a gate dielectric followed by second transistors gate formation step, wherein the second transistors are horizontally oriented.

Abstract translation: 一种用于形成包括第一晶片的半导体器件的方法，所述第一晶片包括包括第一晶体管和第一对准标记的第一单晶层，所述方法包括：注入以在第二晶片内形成掺杂层; 通过使用层转移步骤转移至少一部分掺杂层，在第一晶片的顶部上形成第二单晶层，并且在第二单晶层上完成第二晶体管的形成，包括形成栅极电介质的步骤 随后是第二晶体管栅极形成步骤，其中第二晶体管是水平取向的。

公开(公告)号：US08557632B1

公开(公告)日：2013-10-15

申请号：US13441923

申请日：2012-04-09

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/481 ,  H01L21/743 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/1066 ,  H01L29/66272 ,  H01L29/66704 ,  H01L29/66825 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/808 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/00

Abstract: A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Abstract translation: 一种处理集成电路器件的方法，包括处理第一层第一晶体管，然后处理覆盖第一晶体管的第一金属层，并提供与第一晶体管的至少一个连接，然后处理覆盖第一金属层的第二金属层， 然后处理覆盖第二金属层的第二晶体管的第二层，其中第二金属层被连接以向第二晶体管中的至少一个提供功率。

公开(公告)号：US08536023B2

公开(公告)日：2013-09-17

申请号：US12951913

申请日：2010-11-22

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/78

CPC classification number: H01L21/76254 ,  H01L23/562 ,  H01L29/785 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10253 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/014

Abstract: A method of manufacturing semiconductor wafers, the method including: providing a donor wafer including a semiconductor substrate; performing a lithography step and processing the donor wafer; and performing at least two subsequent steps of layer transfer out of the donor wafer, each layer transfer step producing a transferred layer, where each of the transferred layers had been affected by the lithography step, and where each of the transferred layer includes a plurality of transistors with side gates, and where the layer transfer includes an ion-cut, the ion-cut including an ion implant thru the transistors.

Abstract translation: 一种制造半导体晶片的方法，所述方法包括：提供包括半导体衬底的施主晶片; 执行光刻步骤并处理施主晶片; 并且执行从所述施主晶片进行层传送的至少两个后续步骤，每个层转移步骤产生转移层，其中所述转移层中的每一个都受到光刻步骤的影响，并且其中每个转移层包括多个 具有侧栅的晶体管，并且其中层转移包括离子切割，离子切割包括通过晶体管的离子注入。

公开(公告)号：US08440542B2

公开(公告)日：2013-05-14

申请号：US13218815

申请日：2011-08-26

Applicant: Deepak C. Sekar ,  Zvi Or-Bach

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L21/30

CPC classification number: H01L21/8221 ,  B82Y10/00 ,  H01L21/845 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate; preparing a first monocrystalline layer comprising semiconductor regions; preparing a second monocrystalline layer comprising semiconductor regions overlying the first monocrystalline layer; and etching portions of said first monocrystalline layer and portions of said second monocrystalline layer as part of forming at least one transistor on said first monocrystalline layer.

Abstract translation: 一种制造半导体晶片的方法，所述方法包括：提供包括半导体衬底的基底晶片; 制备包含半导体区域的第一单晶层; 制备包含覆盖在第一单晶层上的半导体区域的第二单晶层; 以及蚀刻所述第一单晶层的部分和所述第二单晶层的部分，作为在所述第一单晶层上形成至少一个晶体管的一部分。

公开(公告)号：US08405420B2

公开(公告)日：2013-03-26

申请号：US12859665

申请日：2010-08-19

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar

IPC: H01L25/00

CPC classification number: H01L21/8221 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/78 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/80001

Abstract: A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

Abstract translation: 系统包括半导体器件。 半导体器件包括第一单晶硅层，其包括第一晶体管，第一对准标记和覆盖在第一单晶硅层上的至少一个金属层，其中所述至少一个金属层比其它材料包括铜或铝; 以及覆盖所述至少一个金属层的第二单晶硅层。 第二单晶硅层包括以基本平行的带布置的多个第二晶体管。 多个频带中的每一个包括沿着重复图案的轴的第二晶体管的一部分。

公开(公告)号：US08379458B1

公开(公告)日：2013-02-19

申请号：US12904124

申请日：2010-10-13

Applicant: Zvi Or-Bach ,  Yuniarto Widjaja ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Yuniarto Widjaja ,  Deepak C. Sekar

IPC: G11C7/10

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/10802 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/1203 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926 ,  H01L2221/6835 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of performing a holding operation to a semiconductor memory array having rows and columns of memory cells by applying an electrical signal to collector regions of multiplicity of said memory cells in parallel, wherein said collector region of said memory cells in a row of said memory array is connected to a common control line, wherein each of said memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein at least one of said memory cells further comprises another memory cell on top thereof; and wherein said holding operation maintains charges stored in said floating body region of multiplicity of memory cells connected to said common control line.

Abstract translation: 一种对具有行和列的存储单元的半导体存储器阵列进行保持操作的方法，该方法是将电信号并行地施加到多个所述存储单元的集电极区域，其中所述存储器单元的所述集电极区域在所述存储器的一行中 阵列连接到公共控制线，其中每个所述存储单元包括限定所述存储器单元的表面的至少一部分的浮动体区域，所述浮体区域具有第一导电类型; 并且其中至少一个所述存储单元还在其顶部还包括另一个存储单元; 并且其中所述保持操作维持存储在连接到所述公共控制线的多个存储单元的所述浮体区域中的电荷。

公开(公告)号：US20120306082A1

公开(公告)日：2012-12-06

申请号：US13571614

申请日：2012-08-10

Applicant: Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/50

CPC classification number: H01L23/3677 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/11807 ,  H01L27/12 ,  H01L29/785 ,  H01L2027/11812 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device, including: a first layer of first transistors, overlaid by at least one interconnection layer, wherein the interconnection layer includes metals such as copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, wherein the second layer is less than about 0.4 micron thick; and a connection path connecting the second transistors to the interconnection layer, wherein the connection path includes at least one through-layer via, and the through-layer via includes material whose co-efficient of thermal expansion is within about 50 percent of the second layer coefficient of thermal expansion.

Abstract translation: 一种器件，包括：由至少一个互连层覆盖的第一晶体管层，其中所述互连层包括诸如铜或铝的金属; 包括第二晶体管的第二层，所述第二层覆盖所述互连层，其中所述第二层小于约0.4微米厚; 以及将所述第二晶体管连接到所述互连层的连接路径，其中所述连接路径包括至少一个通孔，并且所述贯通层通孔包括其热膨胀系数在所述第二层的约50％内的材料 热膨胀系数。

公开(公告)号：US08283215B2

公开(公告)日：2012-10-09

申请号：US12903847

申请日：2010-10-13

Applicant: Zvi Or-Bach ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Deepak C. Sekar

IPC: H01L21/84

CPC classification number: H01L27/15 ,  H01L25/0756 ,  H01L31/0735 ,  H01L31/1844 ,  H01L33/08 ,  H01L33/382 ,  H01L2924/0002 ,  Y02E10/544 ,  H01L2924/00

Abstract: A method for fabricating a light-emitting integrated device, comprises overlying three layers, wherein each of the three layers emits light at a different wavelength, and wherein the overlying comprises one of: performing an atomic species implantation, performing a laser lift-off, performing an etch-back, or chemical-mechanical polishing (CMP).

Abstract translation: 一种制造发光集成装置的方法，包括上述三层，其中三层中的每一层发射不同波长的光，并且其中上覆包括以下之一：执行原子种植入，执行激光剥离， 执行回蚀刻或化学机械抛光（CMP）。