公开(公告)号：US07435684B1

公开(公告)日：2008-10-14

申请号：US11493678

申请日：2006-07-26

Applicant: Chi-I Lang ,  Ratsamee Limdulpaiboon ,  Kan Quan Vo

Inventor： Chi-I Lang ,  Ratsamee Limdulpaiboon ,  Kan Quan Vo

IPC: H01L21/311

CPC classification number: H01L21/02274 ,  C23C16/045 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/31116 ,  H01L21/31604

Abstract: This invention relates to electronic device fabrication processes for making devices such as semiconductor wafers and resolves the fluorine loading effect in the reaction chamber of a HDP CVD apparatus used for forming dielectric layers in high aspect ratio, narrow width recessed features. The fluorine loading effect in the chamber is minimized and wafers are provided having less deposition thickness variations by employing the method using a hydrogen plasma treatment of the chamber and the substrate after the chamber has been used to grow a dielectric film on a substrate. After the hydrogen plasma treatment of the chamber, the chamber is treated with an etchant gas to etch the substrate. Preferably a hydrogen gas is then introduced into the chamber after the etching process and the process repeated until the fabrication process is complete. The wafer is then removed from the chamber and a new wafer placed in the chamber and the above fabrication process repeated.

Abstract translation: 本发明涉及用于制造诸如半导体晶片的器件的电子器件制造工艺，并且解决了用于形成高纵横比，窄宽度凹陷特征的电介质层的HDP CVD装置的反应室中的氟负载效应。 通过使用在腔室已经用于在衬底上生长电介质膜之后使用腔室和衬底的氢等离子体处理的方法，使腔室中的氟负载效应最小化并提供具有较小沉积厚度变化的晶片。 在室的氢等离子体处理之后，用蚀刻剂气体处理该室以蚀刻该衬底。 优选地，在蚀刻工艺之后，将氢气引入室中，重复该过程，直到制造过程完成。 然后将晶片从腔室中取出，并将新的晶片放置在腔室中，并重复上述制造过程。

公开(公告)号：US20080185572A1

公开(公告)日：2008-08-07

申请号：US11702725

申请日：2007-02-05

Applicant: Tony Chiang ,  Chi-I Lang ,  Zhi-wen Sun ,  Jinhong Tong ,  Nitin Kumar

Inventor： Tony Chiang ,  Chi-I Lang ,  Zhi-wen Sun ,  Jinhong Tong ,  Nitin Kumar

IPC: H01L47/00 ,  H01L21/00

CPC classification number: H01L45/04 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

公开(公告)号：US20080185567A1

公开(公告)日：2008-08-07

申请号：US11702966

申请日：2007-02-05

Applicant: Nitin Kumar ,  Chi-I Lang ,  Tony Chiang ,  Zhi-wen Sun ,  Jihhong Tong

Inventor： Nitin Kumar ,  Chi-I Lang ,  Tony Chiang ,  Zhi-wen Sun ,  Jihhong Tong

IPC: H01L47/00 ,  H01L21/00

CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract translation: 提供电阻式开关存储器元件，其可以包含由无电金属形成的化学金属电极和金属氧化物。 电阻式开关存储器元件可以表现出双稳态，并且可以用于高密度多层存储器集成电路中。 诸如镍基材料的无电导电材料可以选择性地沉积在硅晶片或其它合适的衬底上的导体上。 无电导电材料可以被氧化以形成用于电阻式开关存储元件的金属氧化物。 可以沉积多层导电材料，每层具有不同的氧化速率。 可以利用导电层的差异氧化速率来确保在制造期间形成所需厚度的金属氧化物层。

公开(公告)号：US07344996B1

公开(公告)日：2008-03-18

申请号：US11159834

申请日：2005-06-22

Applicant: Chi-I Lang ,  Wenxian Zhu ,  Ratsamee Limdulpaiboon ,  Judy H. Huang

Inventor： Chi-I Lang ,  Wenxian Zhu ,  Ratsamee Limdulpaiboon ,  Judy H. Huang

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76837 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31608

Abstract: Plasma etch processes incorporating helium-based etch chemistries can remove dielectric a semiconductor applications. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate helium as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.

Abstract translation: 掺入氦基蚀刻化学品的等离子体蚀刻工艺可以消除半导体应用的电介质。 特别地，高密度等离子体化学气相蚀刻增强（沉积 - 蚀刻 - 沉积）间隙填充工艺，其结合了氦气作为蚀刻剂的蚀刻化学物质，其可以有效地填充高纵横比间隙，同时减少或消除蚀刻剂化学物质的电介质污染。

公开(公告)号：US20060246737A1

公开(公告)日：2006-11-02

申请号：US11426141

申请日：2006-06-23

Applicant: Kang Yim ,  Melissa Tam ,  Dian Sugiarto ,  Chi-I Lang ,  Peter Lee ,  Li-Qun Xia

Inventor： Kang Yim ,  Melissa Tam ,  Dian Sugiarto ,  Chi-I Lang ,  Peter Lee ,  Li-Qun Xia

IPC: H01L21/31

CPC classification number: H01L21/76834 ,  C23C16/30 ,  C23C16/325 ,  C23C16/401 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832

Abstract: Methods are provided for depositing a silicon carbide layer having significantly reduced current leakage. The silicon carbide layer may be a barrier layer or part of a barrier bilayer that also includes a barrier layer. Methods for depositing oxygen-doped silicon carbide barrier layers are also provided. The silicon carbide layer may be deposited by reacting a gas mixture comprising an organosilicon compound, an aliphatic hydrocarbon comprising a carbon-carbon double bond or a carbon-carbon triple bond, and optionally, helium in a plasma. Alternatively, the silicon carbide layer may be deposited by reacting a gas mixture comprising hydrogen or argon and an organosilicon compound in a plasma.

Abstract translation: 提供了用于沉积具有显着降低的电流泄漏的碳化硅层的方法。 碳化硅层可以是还包括阻挡层的阻挡层或阻挡层双层的一部分。 还提供了沉积氧掺杂的碳化硅阻挡层的方法。 可以通过使包含有机硅化合物，包含碳 - 碳双键或碳 - 碳三键的脂族烃和任选地在等离子体中的氦气的气体混合物反应来沉积碳化硅层。 或者，可以通过在等离子体中使包含氢或氩的气体混合物和有机硅化合物反应来沉积碳化硅层。

公开(公告)号：US06943127B2

公开(公告)日：2005-09-13

申请号：US10302240

申请日：2002-11-22

Applicant: Seon-Mee Cho ,  Peter Wai-Man Lee ,  Chi-I Lang ,  Dian Sugiarto ,  Chen-An Chen ,  Li-Qun Xia ,  Shankar Venkataraman ,  Ellie Yieh

Inventor： Seon-Mee Cho ,  Peter Wai-Man Lee ,  Chi-I Lang ,  Dian Sugiarto ,  Chen-An Chen ,  Li-Qun Xia ,  Shankar Venkataraman ,  Ellie Yieh

IPC: C23C16/30 ,  H01L21/316 ,  H01L21/42

CPC classification number: H01L21/02126 ,  C23C16/30 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  Y10S438/931 ,  Y10T428/31909

Abstract: A low dielectric constant film having silicon-carbon bonds and dielectric constant of about 3.0 or less, preferably about 2.5 or less, is provided. The low dielectric constant film is deposited by reacting a cyclic organosilicon compound and an aliphatic organosilicon compound with an oxidizing gas while applying RF power. The carbon content of the deposited film is between about 10 and about 30 atomic percent excluding hydrogen atoms, and is preferably between about 10 and about 20 atomic percent excluding hydrogen atoms.

Abstract translation: 提供了具有约3.0或更小，优选约2.5或更小的硅 - 碳键和介电常数的低介电常数膜。 通过使环状有机硅化合物和脂族有机硅化合物与氧化气体反应同时施加RF功率来沉积低介电常数膜。 沉积膜的碳含量除氢原子以外约为10至约30原子百分比，优选除氢原子之外约10至约20原子％。

公开(公告)号：US06709715B1

公开(公告)日：2004-03-23

申请号：US09336368

申请日：1999-06-17

Applicant: Chi-I Lang ,  Shin-Puu Jeng ,  Yeming Jim Ma ,  Fong Chang ,  Peter Wai-Man Lee ,  David W. Cheung

Inventor： Chi-I Lang ,  Shin-Puu Jeng ,  Yeming Jim Ma ,  Fong Chang ,  Peter Wai-Man Lee ,  David W. Cheung

IPC: H05H146

CPC classification number: H01L21/3122 ,  B05D1/62 ,  C08G61/025 ,  C08G61/12 ,  C08G2261/3424 ,  C09D4/00 ,  H01J37/32082 ,  H01J37/3244 ,  H01J37/32522 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76807 ,  C08G77/00

Abstract: A method and apparatus for depositing a low dielectric constant film by plasma assisted copolymerization of p-xylylene and a comonomer having carbon-carbon double bonds at a constant RF power level from about 0W to about 100W or a pulsed RF power level from about 20W to about 160W. The copolymer film has a dielectric constant from about 2.2 to about 2.5. Preferred comonomers include tetravinyltetramethylcyclotetrasiloxane, tetraallyloxysilane, and trivinylmethylsilane. The copolymer films include at least 1% by weight of the comonomer.

Abstract translation: 一种用于通过等离子体辅助共聚对苯二甲烯和具有碳 - 碳双键的共聚单体在约0W至约100W的恒定RF功率水平或约20W至约20W的脉冲RF功率水平沉积低介电常数薄膜的方法和装置 约160W。 共聚物膜的介电常数为约2.2至约2.5。 优选的共聚单体包括四乙烯基四甲基环四硅氧烷，四烯丙氧基硅烷和三乙烯基甲基硅烷。 共聚物膜包括至少1重量％的共聚单体。

公开(公告)号：US06413583B1

公开(公告)日：2002-07-02

申请号：US09338470

申请日：1999-06-22

Applicant: Farhad K. Moghadam ,  David W. Cheung ,  Ellie Yieh ,  Li-Qun Xia ,  Wai-Fan Yau ,  Chi-I Lang ,  Shin-Puu Jeng ,  Frederic Gaillard ,  Shankar Venkataraman ,  Srinivas Nemani

Inventor： Farhad K. Moghadam ,  David W. Cheung ,  Ellie Yieh ,  Li-Qun Xia ,  Wai-Fan Yau ,  Chi-I Lang ,  Shin-Puu Jeng ,  Frederic Gaillard ,  Shankar Venkataraman ,  Srinivas Nemani

IPC: C23C1640

CPC classification number: H01L21/02126 ,  C23C16/401 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31053 ,  H01L21/3122 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/76828 ,  H01L21/76834

Abstract: A method for depositing silicon oxide layers having a low dielectric constant by reaction of an organosilicon compound and a hydroxyl forming compound at a substrate temperature less than about 400° C. The low dielectric constant films contain residual carbon and are useful for gap fill layers, pre-metal dielectric layers, inter-metal dielectric layers, and shallow trench isolation dielectric layers in sub-micron devices. The hydroxyl compound can be prepared prior to deposition from water or an organic compound. The silicon oxide layers are preferably deposited at a substrate temperature less than about 40° C. onto a liner layer produced from the organosilicon compound to provide gap fill layers having a dielectric constant less than about 3.0.

Abstract translation: 一种通过在低于约400℃的衬底温度下通过有机硅化合物和羟基形成化合物的反应沉积低介电常数的氧化硅层的方法。低介电常数膜含有残余碳并可用于间隙填充层， 预金属介电层，金属间介电层和亚微米器件中的浅沟槽隔离电介质层。 羟基化合物可以在从水或有机化合物沉积之前制备。 氧化硅层优选在低于约40℃的衬底温度下沉积到由有机硅化合物制备的衬里层上，以提供介电常数小于约3.0的间隙填充层。

公开(公告)号：US6107184A

公开(公告)日：2000-08-22

申请号：US207791

申请日：1998-12-09

Applicant: Robert P. Mandal ,  David Cheung ,  Peter Wai-Man Lee ,  Chi-I Lang

Inventor： Robert P. Mandal ,  David Cheung ,  Peter Wai-Man Lee ,  Chi-I Lang

IPC: B05D7/24 ,  C08G61/02 ,  H01L21/283 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763

CPC classification number: B05D1/60 ,  C08G61/025 ,  H01L21/312 ,  C08G2261/3424 ,  H01L21/31695 ,  Y10S438/958

Abstract: A method and apparatus for forming thin copolymer layers having low dielectric constants on semiconductor substrates includes in situ formation of p-xylylenes, or derivatives thereof, from solid or liquid precursors such as cyclic p-xylylene dimer, p-xylene, 1,4-bis(formatomethyl)benzene, or 1,4-bis(N-methyl-aminomethyl)benzene. P-xylylene is copolymerized with a comonomer having labile groups that are converted to dispersed gas bubbles after the copolymer layer is deposited on the substrate. Preferred comonomers comprise diazocyclopentadienyl, diazoquinoyl, formyloxy, or glyoxyloyloxy groups.

Abstract translation: 用于在半导体衬底上形成具有低介电常数的薄共聚物层的方法和装置包括从固体或液体前体如环状对二甲苯二聚物，对二甲苯，1,4-二甲苯二异氰酸酯原位形成对二甲苯或其衍生物， 双（格式甲基）苯或1,4-双（N-甲基 - 氨基甲基）苯。 在共聚物层沉积在基材上之后，将对二甲苯与具有不稳定基团的共聚单体共聚，转化成分散的气泡。 优选的共聚单体包括重氮环戊二烯基，重氮醌基，甲酰氧基或乙酰氧基合氧基。

公开(公告)号：US08906207B2

公开(公告)日：2014-12-09

申请号：US13081042

申请日：2011-04-06

Applicant: Hong Sheng Yang ,  Chi-I Lang ,  Tony Chiang

Inventor： Hong Sheng Yang ,  Chi-I Lang ,  Tony Chiang

IPC: C23C14/34 ,  C23C14/54 ,  H01J37/34

CPC classification number: C23C14/34 ,  C23C14/54 ,  C23C14/548 ,  H01J37/3447

Abstract: The present disclosure includes a method for control of a film composition with co-sputter physical vapor deposition. In one implementation, the method includes: positioning first and second PVD guns above a substrate, selecting first and second collimators having first and second sets of physical characteristics, positioning the first and second collimators between the first and second PVD guns and the substrate, sputtering at least one material from the first and second PVD guns through the first and second collimators upon application of a first power and second power, wherein the first PVD gun has a first deposition rate from the first collimator at the first power, and the second PVD gun has a second deposition rate from the second collimator at the second power.

Abstract translation: 本公开内容包括用于控制具有共溅射物理气相沉积的膜组合物的方法。 在一个实施方案中，该方法包括：将第一和第二PVD枪定位在衬底上方，选择具有第一和第二组物理特性的第一和第二准直器，将第一和第二准直器定位在第一和第二PVD枪和衬底之间，溅射 在施加第一功率和第二功率时，来自第一和第二PVD枪的至少一种材料通过第一和第二准直器，其中第一PVD枪具有来自第一准直器的第一沉积速率，而第二PVD 枪在第二功率下具有来自第二准直器的第二沉积速率。