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    Recessed gate for an image sensor
    21.
    发明授权
    Recessed gate for an image sensor 有权
    嵌入式门用于图像传感器

    公开(公告)号：US07217968B2

    公开(公告)日：2007-05-15

    申请号：US10905097

    申请日：2004-12-15

    Applicant: James W. Adkisson ,  John Ellis-Monaghan ,  Mark D. Jaffe ,  Jerome B. Lasky

    Inventor： James W. Adkisson ,  John Ellis-Monaghan ,  Mark D. Jaffe ,  Jerome B. Lasky

    IPC: H01L31/062

    CPC classification number: H01L27/14603 ,  H01L27/14601 ,  H01L27/14689 ,  H01L29/66621

    Abstract: A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.

    Abstract translation: 一种新颖的图像传感器单元结构及其制造方法。 成像传感器包括基板，包括电介质层和形成在电介质层上的栅极导体的栅极，形成在与栅极导体的第一侧相邻的基板的表面下面的第一导电类型的收集阱层，钉扎层 在基板表面上形成在集合阱顶部的第二导电类型的第一导电类型的扩散区和在栅极导体的第二侧附近形成的第一导电类型的扩散区，栅极导体在集电阱层和扩散区之间形成沟道区 。 栅极导体底部的一部分凹陷在基板的表面下方。 优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到使得收集阱与沟道区相交的深度。

    Methods for enhancing quality of pixel sensor image frames for global shutter imaging
    23.
    发明授权
    Methods for enhancing quality of pixel sensor image frames for global shutter imaging 有权
    用于提高全局快门成像的像素传感器图像帧质量的方法

    公开(公告)号：US08681254B2

    公开(公告)日：2014-03-25

    申请号：US13283819

    申请日：2011-10-28

    Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe

    Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe

    IPC: H04N3/14 ,  H04N5/335 ,  H04N9/64 ,  H01L31/062 ,  H01L31/113

    CPC classification number: H04N5/361 ,  H04N5/359

    Abstract: The image qualify of an image frame from a CMOS image sensor array operated in global shutter mode may be enhanced by dispersing or randomizing the noise introduced by leakage currents from floating drains among the rows of the image frame. Further, the image quality may be improved by accounting for time dependent changes in the output of dark pixels in dark pixel rows or dark pixel columns. In addition, voltage and time dependent changes in the output of dark pixels may also be measured to provide an accurate estimate of the noise introduced to the charge held in the floating drains. Such methods may be employed individually or in combination to improve the quality of the image.

    Abstract translation: 来自在全球快门模式下操作的CMOS图像传感器阵列的图像帧的图像限定可以通过将来自浮动排水口的泄漏电流引入的噪声分散或随机化在图像帧的行中来增强。 此外，通过考虑暗像素行或暗像素列中的暗像素的输出中的时间依赖性变化，可以提高图像质量。 此外，还可以测量暗像素的输出中的电压和时间相关的变化，以提供引入到浮动排水管中的电荷的噪声的准确估计。 这样的方法可以单独使用或组合使用以提高图像的质量。

    Three dimensional vertical E-fuse structures and methods of manufacturing the same
    27.
    发明授权
    Three dimensional vertical E-fuse structures and methods of manufacturing the same 失效
    三维垂直E熔丝结构及其制造方法

    公开(公告)号：US08232190B2

    公开(公告)日：2012-07-31

    申请号：US11865079

    申请日：2007-10-01

    Applicant: Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

    Inventor： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

    IPC: H01L21/44

    CPC classification number: H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.

    Abstract translation: 本文提供三维垂直电子熔丝结构及其制造方法。 形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。 该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。 垂直e熔丝结构包括第一接触层和第二接触层。 该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。 当施加电流时，导电材料具有增加的电阻。

    CMOS imager photodiode with enhanced capacitance
    28.
    发明授权
    CMOS imager photodiode with enhanced capacitance 有权
    具有增强电容的CMOS成像光电二极管

    公开(公告)号：US08106432B2

    公开(公告)日：2012-01-31

    申请号：US12634898

    申请日：2009-12-10

    Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

    Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

    IPC: H01L31/04

    CPC classification number: H01L27/14643 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/035281

    Abstract: A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.

    Abstract translation: 一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。 感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间并形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离， 基材表面。 在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于在衬底表面形成的掺杂层的下方。

    ISOLATION WITH OFFSET DEEP WELL IMPLANTS
    29.
    发明申请
    ISOLATION WITH OFFSET DEEP WELL IMPLANTS 审中-公开
    隔离深度较深的植入物

    公开(公告)号：US20120001268A1

    公开(公告)日：2012-01-05

    申请号：US13228998

    申请日：2011-09-09

    Applicant: James W. Adkisson ,  Andres Bryant ,  Mark D. Jaffe ,  Alain Loiseau

    Inventor： James W. Adkisson ,  Andres Bryant ,  Mark D. Jaffe ,  Alain Loiseau

    IPC: H01L27/092

    CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/823892

    Abstract: A method implants impurities into well regions of transistors. The method prepares a first mask over a substrate and performs a first shallow well implant through the first mask to implant first-type impurities to a first depth of the substrate. The first mask is removed and a second mask is prepared over the substrate. The method performs a second shallow well implant through the second mask to implant second-type impurities to the first depth of the substrate and then removes the second mask. A third mask is prepared over the substrate. The third mask has openings smaller than openings in the first mask and the second mask. A first deep well implant is performed through the third mask to implant the first-type impurities to a second depth of the substrate, the second depth of the substrate being greater than the first depth of the substrate. The third mask is removed and a fourth mask is prepared over the substrate, the fourth mask has openings smaller than the openings in the first mask and the second mask. Then, a second deep well implant is performed through the fourth mask to implant the second-type impurities to the second depth of the substrate.

    Abstract translation: 一种方法是将杂质掺入晶体管的阱区。 该方法在衬底上制备第一掩模，并且通过第一掩模执行第一浅阱注入，以将第一类型的杂质注入衬底的第一深度。 去除第一个掩模，并在衬底上制备第二个掩模。 该方法通过第二掩模执行第二浅井注入，以将第二类型杂质植入衬底的第一深度，然后移除第二掩模。 在衬底上制备第三个掩模。 第三掩模具有比第一掩模和第二掩模中的开口小的开口。 通过第三掩模执行第一深孔注入，以将第一类型的杂质注入衬底的第二深度，衬底的第二深度大于衬底的第一深度。 去除第三掩模并在衬底上制备第四掩模，第四掩模具有小于第一掩模和第二掩模中的开口的开口。 然后，通过第四掩模进行第二深孔注入，以将第二类型的杂质植入到衬底的第二深度。

    High efficiency CMOS image sensor pixel employing dynamic voltage supply
    30.
    发明授权
    High efficiency CMOS image sensor pixel employing dynamic voltage supply 失效
    采用动态电压源的高效率CMOS图像传感器像素

    公开(公告)号：US08023021B2

    公开(公告)日：2011-09-20

    申请号：US12641589

    申请日：2009-12-18

    Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante ,  Richard J. Rassel

    Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante ,  Richard J. Rassel

    IPC: H04N5/335

    CPC classification number: H04N5/361 ,  G06F17/5063 ,  H04N5/359 ,  H04N5/3745

    Abstract: A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.

    Abstract translation: 提供了包括复位栅极（RG）晶体管的全局快门兼容像素电路，其中动态电压被施加到复位栅极晶体管的漏极，以便减少在信号保持时间期间通过其的浮动扩散（FD）泄漏。 复位栅极晶体管的漏极电压保持在比电路电源电压更低的电压，以最小化通过RG晶体管的截止状态泄漏，从而减少信号保持时间期间浮动扩散时的电压变化。 此外，还提供了用于向像素电路的复位栅极的漏极提供动态电压的这种电路的设计结构。

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