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    Semi-static power and performance optimization of data centers
    21.
    发明授权
    Semi-static power and performance optimization of data centers 有权
    数据中心的半静态功耗和性能优化

    公开(公告)号：US09116703B2

    公开(公告)日：2015-08-25

    申请号：US13651904

    申请日：2012-10-15

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Mauricio Breternitz ,  Leonardo Piga

    IPC: G06F1/32 ,  G06F9/50 ,  G06T7/20

    CPC classification number: G06F1/329 ,  G06F9/5094 ,  G06F2209/501 ,  Y02D10/22 ,  Y02D10/24

    Abstract: A device may receive information that identifies a first task to be processed, may determine a performance metric value indicative of a behavior of a processor while processing a second task, and may assign, based on the performance metric value, the first task to a bin for processing the first task, the bin including a set of processors that operate based on a power characteristic.

    Abstract translation: 设备可以接收标识待处理的第一任务的信息，可以在处理第二任务时确定指示处理器的行为的性能度量值，并且可以基于性能度量值将第一任务分配给bin 用于处理第一任务，该仓包括基于功率特性操作的一组处理器。

    THREAD ASSIGNMENT FOR POWER AND PERFORMANCE EFFICIENCY USING MULTIPLE POWER STATES
    22.
    发明申请
    THREAD ASSIGNMENT FOR POWER AND PERFORMANCE EFFICIENCY USING MULTIPLE POWER STATES 有权
    使用多个电力状态的电力和性能效率的螺纹分配

    公开(公告)号：US20140359633A1

    公开(公告)日：2014-12-04

    申请号：US13909789

    申请日：2013-06-04

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Mauricio Breternitz ,  Leonardo Piga

    IPC: G06F9/50

    CPC classification number: G06F9/5094 ,  G06F1/32 ,  G06F1/329 ,  G06F9/4893 ,  G06F9/5088 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D10/32

    Abstract: A method is performed in a computing system that includes a plurality of processing nodes of multiple types configurable to run in multiple performance states. In the method, an application executes on a thread assigned to a first processing node. Power and performance of the application on the first processing node is estimated. Power and performance of the application in multiple performance states on other processing nodes of the plurality of processing nodes besides the first processing node is also estimated. It is determined that the estimated power and performance of the application on a second processing node in a respective performance state of the multiple performance states is preferable to the power and performance of the application on the first processing node. The thread is reassigned to the second processing node, with the second processing node in the respective performance state.

    Abstract translation: 在计算系统中执行一种方法，该计算系统包括多个可配置为以多个执行状态运行的多个处理节点。 在该方法中，应用程序在分配给第一处理节点的线程上执行。 估计第一处理节点上的应用的功率和性能。 还估计除了第一处理节点之外的多个处理节点的其他处理节点上的多个性能状态下的应用的功率和性能。 确定在多个性能状态的各个性能状态下的第二处理节点上的应用的估计功率和性能优于第一处理节点上的应用的功率和性能。 线程被重新分配给第二处理节点，其中第二处理节点处于相应的执行状态。

    Tracking Non-Native Content in Caches
    23.
    发明申请
    Tracking Non-Native Content in Caches 审中-公开
    跟踪缓存中的非本地内容

    公开(公告)号：US20140156941A1

    公开(公告)日：2014-06-05

    申请号：US13691375

    申请日：2012-11-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Gabriel H. Loh ,  Mithuna S. Thottehodi ,  Yasuko Eckert ,  James M. O'Connor ,  Mauricio Breternitz ,  Bradford M. Beckmann ,  Nuwan Jayasena

    IPC: G06F12/08

    CPC classification number: G06F12/0895 ,  G06F1/3275 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/502 ,  Y02D10/124 ,  Y02D10/13 ,  Y02D10/14

    Abstract: The described embodiments include a cache with a plurality of banks that includes a cache controller. In these embodiments, the cache controller determines a value representing non-native cache blocks stored in at least one bank in the cache, wherein a cache block is non-native to a bank when a home for the cache block is in a predetermined location relative to the bank. Then, based on the value representing non-native cache blocks stored in the at least one bank, the cache controller determines at least one bank in the cache to be transitioned from a first power mode to a second power mode. Next, the cache controller transitions the determined at least one bank in the cache from the first power mode to the second power mode.

    Abstract translation: 所描述的实施例包括具有包括高速缓存控制器的多个存储体的高速缓存。 在这些实施例中，高速缓存控制器确定表示存储在高速缓存中的至少一个存储区中的非本机高速缓存块的值，其中当高速缓存块的归属位于相对于预定位置时，高速缓存块对于存储体是非本地的 去银行。 然后，高速缓存控制器基于代表存储在至少一个存储体中的非本地高速缓存块的值，确定高速缓存中的至少一个存储体将从第一功率模式转换到第二功率模式。 接下来，高速缓存控制器将所确定的高速缓存中的至少一个存储体从第一功率模式转换到第二功率模式。

    ENHANCED RESOLUTION VIDEO AND SECURITY VIA MACHINE LEARNING
    25.
    发明申请
    ENHANCED RESOLUTION VIDEO AND SECURITY VIA MACHINE LEARNING 审中-公开

    公开(公告)号：US20180295320A1

    公开(公告)日：2018-10-11

    申请号：US15485071

    申请日：2017-04-11

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Mauricio Breternitz ,  John E. Owen, JR.

    IPC: H04N7/01 ,  H04L29/06

    CPC classification number: H04N7/0117 ,  G06T3/40 ,  H04L63/0428 ,  H04L2209/34

    Abstract: Systems, apparatuses, and methods for enhanced resolution video and security via machine learning are disclosed. A transmitter reduces a resolution of each image of a videostream from a first, higher image resolution to a second, lower image resolution. The transmitter generates a set of parameters for programming a neural network to reconstruct a version of each image at the first image resolution. Then, the transmitter sends the images at the second image resolution to the receiver, along with the first set of parameters. The receiver programs a neural network with the first set of parameters and uses the neural network to reconstruct versions of the images at the first image resolution. The transmitter can send the first set of parameters to the receiver via a secure channel, ensuring that only the receiver can decode the images from the second image resolution to the first image resolution.

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