公开(公告)号：US09530638B2

公开(公告)日：2016-12-27

申请号：US14870792

申请日：2015-09-30

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Hua Chung ,  Jenn-Yue Wang ,  Xuebin Li ,  Yi-Chiau Huang ,  Schubert S. Chu

IPC: H01L21/20 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/7848 ,  H01L29/7851

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

Abstract translation: 本公开的实施方式一般涉及在外延膜上硅材料外延生长的方法。 在一个实施方案中，该方法包括在半导体鳍片上形成外延膜，其中外延膜包括具有第一面和第二面的顶表面，并且通过交替地在至少外延膜的顶表面上形成外延层 将顶表面暴露于包含一种或多种硅烷的第一前体气体和包含一种或多种氯化硅烷的第二前体气体，其温度为约375℃至约450℃，室压力为约5托至约 20乇

公开(公告)号：US09530637B2

公开(公告)日：2016-12-27

申请号：US14875013

申请日：2015-10-05

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Hua Chung

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8258

CPC classification number: H01L21/02507 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/8258

Abstract: Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET manufacturing without the utilization of multiple patterning processes. Embodiments described herein also provide for fin material manufacturing methods for transitioning from silicon to III-V materials while maintaining acceptable crystal lattice orientations of the various materials utilized. Further embodiments provide etching apparatus which may be utilized to perform the methods described herein.

Abstract translation: 提供了用于形成FinFET结构的方法和装置。 本文所述的选择性蚀刻和沉积工艺可以提供FinFET制造而不利用多个图案化工艺。 本文描述的实施例还提供了用于从硅转变为III-V材料的翅片材料制造方法，同时保持所使用的各种材料的可接受的晶格取向。 另外的实施例提供可用于执行本文所述方法的蚀刻装置。

公开(公告)号：US11384429B2

公开(公告)日：2022-07-12

申请号：US15598687

申请日：2017-05-18

Applicant: Applied Materials, Inc.

Inventor： Sang-Ho Yu ,  Kevin Moraes ,  Seshadri Ganguli ,  Hua Chung ,  See-Eng Phan

IPC: C23C16/16 ,  H01L21/324 ,  H01L21/768 ,  C23C16/02 ,  C23C16/18 ,  H01L21/02 ,  H01L21/285 ,  C23C16/455 ,  C23C16/50

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface. In another embodiment, a deposition-treatment cycle includes performing the vapor deposition process and subsequently a post-treatment process, which deposition-treatment cycle may be repeated to form multiple cobalt capping layers.

公开(公告)号：US11164767B2

公开(公告)日：2021-11-02

申请号：US16591354

申请日：2019-10-02

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/67 ,  H01J37/32 ,  B08B7/00 ,  C30B25/04 ,  C30B25/18 ,  C30B29/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3065 ,  H01L29/66

Abstract: Implementations of the present disclosure generally relate to methods and apparatuses for epitaxial deposition on substrate surfaces. More particularly, implementations of the present disclosure generally relate to an integrated system for processing N-type metal-oxide semiconductor (NMOS) devices. In one implementation, a cluster tool for processing a substrate is provided. The cluster tool includes a pre-clean chamber, an etch chamber, one or more pass through chambers, one or more outgassing chambers, a first transfer chamber, a second transfer chamber, and one or more process chambers. The pre-clean chamber and the etch chamber are coupled to a first transfer chamber. The one or more pass through chambers are coupled to and disposed between the first transfer chamber and the second transfer chamber. The one or more outgassing chambers are coupled to the second transfer chamber. The one or more process chambers are coupled to the second transfer chamber.

公开(公告)号：US10276688B2

公开(公告)日：2019-04-30

申请号：US15896983

申请日：2018-02-14

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Zhiyuan Ye ,  Flora Fong-Song Chang ,  Abhishek Dube ,  Xuebin Li ,  Errol Antonio C. Sanchez ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L29/417 ,  H01L21/02

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

公开(公告)号：US10115607B2

公开(公告)日：2018-10-30

申请号：US15267232

申请日：2016-09-16

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Chun Yan ,  Hua Chung ,  Schubert S. Chu

IPC: B65B31/00 ,  H01L21/67 ,  H01L21/673 ,  H01L21/677

Abstract: Embodiments disclosed herein generally relate to apparatus and methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a Si:As process has been performed on a substrate, and prior to additional processing. The apparatus includes a purge station including an enclosure, a gas supply coupled to the enclosure, an exhaust pump coupled to the enclosure, a first purge gas port formed in the enclosure, a first channel operatively connected to the gas supply at a first end and to the first purge gas port at a second end, a second purge gas port formed in the enclosure, and a second channel operatively connected to the second purge gas port at a third end and to the exhaust pump at a fourth end. The first channel includes a particle filter, a heater, and a flow controller. The second channel includes a dry scrubber.

公开(公告)号：US09966271B2

公开(公告)日：2018-05-08

申请号：US15345549

申请日：2016-11-08

Applicant: Applied Materials, Inc.

Inventor： Wei Liu ,  Hua Chung ,  Xuebin Li ,  Yuxiang Lu

IPC: H01L21/302 ,  H01L21/3065 ,  H01J37/32 ,  H01L21/308 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/3065 ,  H01J37/32009 ,  H01J37/3244 ,  H01J2237/334 ,  H01L21/02115 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02274 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3083 ,  H01L29/66795

Abstract: Methods for forming semiconductor devices, such as FinFET devices, are provided. An epitaxial film is formed over a semiconductor fin, and the epitaxial film includes a top surface having two facets and a bottom surface including two facets. A cap layer is deposited on the top surface, and portions of the epitaxial film in a lateral direction are removed by an isotropic plasma etch process. The isotropic plasma etch process may be performed at a pressure ranging from about 5 mTorr to about 200 mTorr in order to maximize the amount of radicals while minimizing the amount of ions in the plasma. Having a smaller lateral dimension prevents the epitaxial film from merging with an adjacent epitaxial film and creates a gap between the epitaxial film and the adjacent epitaxial film.

公开(公告)号：US09923081B1

公开(公告)日：2018-03-20

申请号：US15479091

申请日：2017-04-04

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Zhiyuan Ye ,  Flora Fong-Song Chang ,  Abhishek Dube ,  Xuebin Li ,  Errol Antonio C. Sanchez ,  Hua Chung ,  Schubert S. Chu

IPC: H01L23/48 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167

CPC classification number: H01L29/6659 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7851

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

公开(公告)号：US09553147B2

公开(公告)日：2017-01-24

申请号：US14673033

申请日：2015-03-30

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Hua Chung

IPC: H01L21/302 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L29/1037 ,  H01L21/02538 ,  H01L21/265 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/66795 ,  H01L29/7848

Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

Abstract translation: 本文描述的实施例通常涉及形成次10nm节点FinFET的方法。 可以在衬底上执行各种处理步骤，以提供在其上共形沉积介电层的沟槽。 随后在沟槽内蚀刻电介质层以暴露下面的衬底，并且半导体材料沉积在沟槽中以形成鳍结构。 形成沟槽，沉积介电层和形成鳍结构的工艺可以实现10nm以下的节点尺寸并提供越来越小的FinFET。

公开(公告)号：US09548201B2

公开(公告)日：2017-01-17

申请号：US14730194

申请日：2015-06-03

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Uday Mitra ,  Praburam Gopalraja ,  Srinivas D. Nemani ,  Hua Chung

IPC: H01L23/58 ,  H01L23/544 ,  H01L21/302 ,  H01L21/461 ,  H01L21/033 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816

Abstract: The present disclosure provides forming nanostructures with precision dimension control and minimum lithographic related errors for features with dimension under 14 nanometers and beyond. A self-aligned multiple spacer patterning (SAMSP) process is provided herein and the process utilizes minimum lithographic exposure process, but rather multiple deposition/etching process to incrementally reduce feature sizes formed in the mask along the manufacturing process, until a desired extreme small dimension nanostructures are formed in a mask layer.

Abstract translation: 本公开提供形成具有尺寸在14纳米以下的特征的精确尺寸控制和最小光刻相关误差的纳米结构。 本文提供了自对准多间隔图案（SAMSP）工艺，并且该工艺利用最小光刻曝光工艺，而是采用多次沉积/蚀刻工艺来逐渐减小沿制造工艺在掩模中形成的特征尺寸，直到期望的极小尺寸 在掩模层中形成纳米结构。