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    Testing architecture of circuits integrated on a wafer
    23.
    发明授权
    Testing architecture of circuits integrated on a wafer 有权
    集成在晶圆上的电路的测试架构

    公开(公告)号：US09541601B2

    公开(公告)日：2017-01-10

    申请号：US13554133

    申请日：2012-07-20

    Applicant: Alberto Pagani

    Inventor： Alberto Pagani

    IPC: H01L23/58 ,  H01L29/10 ,  G01R31/28 ,  H01L21/66 ,  H01L23/00

    CPC classification number: G01R31/2884 ,  H01L22/32 ,  H01L22/34 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05554 ,  H01L2924/12042 ,  H01L2924/00

    Abstract: An embodiment of a testing architecture of integrated circuits on a wafer is described of the type including at least one first circuit of a structure TEG realized in a scribe line providing separation between at least one first and one second integrated circuit. The architecture includes at least one pad shared by a second circuit inside at least one of these first and second integrated circuit and the first circuit, as well as a switching circuitry coupled to the at least one pad and to these first and second circuits.

    Abstract translation: 描述了晶片上的集成电路的测试架构的实施例，其包括在划线中实现的结构TEG的至少一个第一电路，其提供至少一个第一和第二集成电路之间的间隔。 该架构包括在这些第一和第二集成电路和第一电路中的至少一个内的第二电路共享的至少一个焊盘，以及耦合到至少一个焊盘和这些第一和第二电路的开关电路。

    Signal transmission through LC resonant circuits
    24.
    发明授权
    Signal transmission through LC resonant circuits 有权
    通过LC谐振电路进行信号传输

    公开(公告)号：US08902016B2

    公开(公告)日：2014-12-02

    申请号：US12907812

    申请日：2010-10-19

    Applicant: Alberto Pagani

    Inventor： Alberto Pagani

    IPC: H01P5/04 ,  H04B5/00 ,  H01P5/00

    CPC classification number: H01F38/14 ,  H01F2038/146 ,  H02J17/00 ,  H02J50/05 ,  H02J50/10 ,  H02J50/40 ,  H02J50/70 ,  H02J50/80 ,  H04B5/0012 ,  H04B5/0037 ,  H04B5/0075 ,  H04B5/0093

    Abstract: An embodiment of an electronic system includes a first electronic circuit and a second electronic circuit. The electronic system further includes a resonant LC circuit having a resonance frequency for coupling the first electronic circuit and the second electronic circuit; each electronic circuit includes functional means for providing a signal at the resonance frequency to be transmitted to the other electronic circuit through the LC circuit and/or for receiving the signal from the other electronic circuit. The LC circuit also include capacitor means having at least one first capacitor plate included in the first electronic circuit and at least one second capacitor plate included in the second electronic circuit. The LC circuit further includes first inductor means included in the first electronic circuit and/or second inductor means included in the second electronic circuit. The at least one capacitor plate of each electronic circuit is coupled with the corresponding functional means through the possible corresponding inductor means.

    Abstract translation: 电子系统的实施例包括第一电子电路和第二电子电路。 电子系统还包括具有用于耦合第一电子电路和第二电子电路的谐振频率的谐振LC电路; 每个电子电路包括用于提供谐振频率的信号的功能装置，以通过LC电路传输到另一电子电路和/或用于从另一电子电路接收信号。 LC电路还包括具有包括在第一电子电路中的至少一个第一电容器板和包括在第二电子电路中的至少一个第二电容器板的电容器装置。 LC电路还包括包括在第一电子电路中的第一电感器装置和/或包括在第二电子电路中的第二电感器装置。 每个电子电路的至少一个电容器板通过可能的相应的电感器装置与相应的功能装置耦合。

    Testing of electronic devices through capacitive interface
    25.
    发明授权
    Testing of electronic devices through capacitive interface 有权
    通过电容接口测试电子设备

    公开(公告)号：US08791711B2

    公开(公告)日：2014-07-29

    申请号：US12907839

    申请日：2010-10-19

    Applicant: Alberto Pagani

    Inventor： Alberto Pagani

    IPC: G01R31/20 ,  G01R1/07 ,  G01R1/073 ,  G01R31/312

    CPC classification number: G01R1/06761 ,  G01R1/06711 ,  G01R1/06716 ,  G01R1/06733 ,  G01R1/06766 ,  G01R1/07 ,  G01R1/07314 ,  G01R31/312

    Abstract: An embodiment of a test apparatus for executing a test of a set of electronic devices having a plurality of electrically conductive terminals, the test apparatus including a plurality of electrically conductive test probes for exchanging electrical signals with the terminals, and coupling means for mechanically coupling the test probes with the electronic devices. In an embodiment, the coupling means includes insulating means for keeping each one of at least part of the test probes electrically insulated from at least one corresponding terminal during the execution of the test. Each test probe and the corresponding terminal form a capacitor for electro-magnetically coupling the test probe with the terminal.

    Abstract translation: 一种用于执行具有多个导电端子的电子装置的测试的测试装置的实施例，所述测试装置包括用于与端子交换电信号的多个导电测试探针，以及用于机械耦合 用电子设备测试探头。 在一个实施例中，耦合装置包括绝缘装置，用于在执行测试期间将至少部分测试探针中的每一个与至少一个相应的端子电绝缘。 每个测试探头和相应的端子形成用于将测试探头与端子电磁耦合的电容器。

    Process for making an electric testing of electronic devices
    27.
    发明授权
    Process for making an electric testing of electronic devices 有权
    进行电子设备电气测试的过程

    公开(公告)号：US08479066B2

    公开(公告)日：2013-07-02

    申请号：US13027617

    申请日：2011-02-15

    Applicant: Alberto Pagani

    Inventor： Alberto Pagani

    IPC: G01R31/28

    CPC classification number: G01R31/31908 ,  G01R31/3025 ,  G01R31/318572 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A process for electrically testing electronic devices includes connecting at least one electronic device to an automatic testing apparatus suitable for testing digital circuits, and sending, through the apparatus, control signals for electrically testing the electronic device. The process further includes electrically testing the electronic device through at least one reconfigurable digital interface connected to the apparatus through a dedicated digital communication channel and comprising a limited number of communication or connection lines strictly appointed to the exchange of the testing information. Response messages are sent from the electronic device to the apparatus through the digital communication channel in response to the control signals. The response messages contain mesaurements, failure information, and data.

    Abstract translation: 用于电测试电子设备的过程包括将至少一个电子设备连接到适合于测试数字电路的自动测试设备，以及通过设备发送用于电测试电子设备的控制信号。 该方法还包括通过至少一个通过专用数字通信信道连接到该设备的可重新配置数字接口电测试电子设备，并且包括严格指定用于测试信息交换的有限数量的通信或连接线。 响应于控制信号，响应消息通过数字通信信道从电子设备发送到设备。 响应消息包含mesaurements，故障信息和数据。

    METHOD FOR AN IMPROVED CHECKING OF REPEATABILITY AND REPRODUCIBILITY OF A MEASURING CHAIN FOR SEMICONDUCTOR DEVICE TESTING
    28.
    发明申请
    METHOD FOR AN IMPROVED CHECKING OF REPEATABILITY AND REPRODUCIBILITY OF A MEASURING CHAIN FOR SEMICONDUCTOR DEVICE TESTING 有权
    用于半导体器件测试的测量链的可重复性和可重复性的改进方法

    公开(公告)号：US20110254580A1

    公开(公告)日：2011-10-20

    申请号：US13092772

    申请日：2011-04-22

    Applicant: Sergio Tenucci ,  Alberto Pagani ,  Marco Spinetta ,  Bernard Ranchoux

    Inventor： Sergio Tenucci ,  Alberto Pagani ,  Marco Spinetta ,  Bernard Ranchoux

    IPC: G01R31/26 ,  G06F19/00

    CPC classification number: G05B19/41875 ,  G01R31/2894 ,  Y02P90/22 ,  Y02P90/86

    Abstract: A method provides an improved checking of repeatability and reproducibility of a measuring chain, in particular for quality control by semiconductor device testing. The method includes testing steps provided for multiple and different devices to be subjected to measurement or control through a measuring system that includes at least one chain of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement or control. Advantageously, the method comprises checking repeatability and reproducibility of each type of unit that forms part of the measuring chain and, after the checking, making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement or control.

    Abstract translation: 一种方法提供了对测量链的重复性和再现性的改进的检查，特别是通过半导体器件测试的质量控制。 该方法包括对通过测量系统进行测量或控制的多个和不同设备提供的测试步骤，所述测量系统包括测试装置（ATE）和要进行测量或控制的每个设备之间的至少一个测量单元链。 有利地，该方法包括检查构成测量链的一部分的每种类型的单元的重复性和再现性，并且在检查之后，使各种测量链之间的相关性作为整体来检查重复性和再现性，使用受到 测量或控制。

    Crosstalk suppression in wireless testing of semiconductor devices
    29.
    发明授权
    Crosstalk suppression in wireless testing of semiconductor devices 有权
    半导体器件无线测试中的串扰抑制

    公开(公告)号：US07915908B2

    公开(公告)日：2011-03-29

    申请号：US12037319

    申请日：2008-02-26

    Applicant: Alberto Pagani

    Inventor： Alberto Pagani

    IPC: G01R31/02 ,  G01R31/26

    CPC classification number: G01R31/2851 ,  G01R31/2886 ,  G01R31/3025 ,  G01R31/303 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.

    Abstract translation: 一种集成在半导体材料裸片上并适于至少部分地被无线测试的集成电路，其中用于设置用于集成电路的无线测试的所选无线电通信频率的电路集成在半导体材料裸片上。

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