公开(公告)号：US20240411057A1

公开(公告)日：2024-12-12

申请号：US18632562

申请日：2024-04-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Raphaël FEOUGIER ,  Nicolas POSSEME ,  Raluca TIRON ,  Maxime ARGOUD

IPC: G02B3/00 ,  B81C1/00

Abstract: A method for manufacturing a three-dimensional structure comprising supplying a stack comprising, stacked in a vertical direction, a support substrate, a sacrificial layer, a layer of interest having a sidewall and a tensor layer having a sidewall, the tensor layer having a residual stress. The method also comprises removing a removal portion of the sacrificial layer, while retaining a remaining portion of the sacrificial layer underlying the layer of interest. The removal portion is located in line with a lateral portion of the layer of interest extending from the entire sidewall of the layer of interest. The residual stress of the tensor layer is configured to cause bending of the layer of interest during the step of removing the removal portion.

公开(公告)号：US20240063058A1

公开(公告)日：2024-02-22

申请号：US18350990

申请日：2023-07-12

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Stefan LANDIS

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/544

CPC classification number: H01L21/76877 ,  H01L21/823475 ,  H01L21/76802 ,  H01L23/544 ,  H01L2223/5444

Abstract: The invention is based on a method for producing an individualisation zone of a chip comprising a component level and a contact level comprising vias, the method comprising the following steps:



providing the components level and a dielectric layer,
forming a mask on the dielectric layer,
etching the dielectric layer through mask openings so as to form openings opening onto the contact zones of the components level,
forming fluorinated residue by inputting fluorinated species on at least some contact zones, the openings thus comprising openings with fluorinated residue and openings without residue,
filling the openings so as to form the vias of the contact level, said vias comprising functional vias at the openings without residue and altered vias at the openings with residue.

公开(公告)号：US20230210021A1

公开(公告)日：2023-06-29

申请号：US18056318

申请日：2022-11-17

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Cyrille LE ROYER ,  Fabrice NEMOUCHI ,  Roselyne SEGAUD

IPC: H10N60/85 ,  H10N60/01

CPC classification number: H10N60/85 ,  H10N60/0156

Abstract: The invention concerns an inteconnect device for interconnection between lines of superconducting material at least one via in contact with those lines, comprising:
a) a first substrate, which carries at least one first line of a first superconducting material;

b) at least one first via of a second superconducting material, different from the first superconducting material, said at least one first line being disposed between said first substrate and said first via;

c) at least one second line above said first via and in contact with the latter.

公开(公告)号：US20220270880A1

公开(公告)日：2022-08-25

申请号：US17652324

申请日：2022-02-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Valentin BACQUIE ,  Nicolas POSSEME

IPC: H01L21/28 ,  H01L21/3115

Abstract: A method is provided for forming spacers of a gate of a transistor, including: providing an active layer surmounted by a gate; forming a dielectric layer covering the gate and the active layer, the dielectric layer having lateral portions and basal portions; anisotropically modifying the basal portions by implantation of light ions, forming modified basal portions; and removing the modified basal portions by selective etching, so as to form the spacers on the lateral flanks of the gate from the unmodified lateral portions, in which, before the removing step, the anisotropic modification of the basal portions includes n successive implantation phases having implantation energies Γi (i=1 . . . n) which are distinct from each other, the n phases being configured to implant the light ions at different nominal implantation depths.

公开(公告)号：US20220028802A1

公开(公告)日：2022-01-27

申请号：US17443131

申请日：2021-07-21

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Stefan LANDIS ,  Hubert TEYSSEDRE

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033

Abstract: The invention relates to a method for making an individualization zone of a microchip comprising a first (10A) and a second (20A) level of electrical tracks (10, 20), and a conductor layer (30A) comprising via holes (30), the method comprising the following steps: providing at least one dielectric layer (200, 201, 202) having a thickness hd, forming a metal mask layer (300) having a thickness hm and a residual stress σr on the at least one dielectric layer (200, 201, 202), etching the layer (300) so as to form line patterns (310) of width l, etching the at least one dielectric layer (200, 201, 202) between the line patterns (310) so as to form trenches (210) separated by walls (211), filling the trenches (210) with an electrically conductive material so as to form the electrical tracks (10, 10KO) of the first level (10A), forming via holes (30, 30OK, 30KO1, 30KO2) of the conductor layer (30A), forming the second level (20A) of electrical tracks (20, 20OK), the method being characterized in that the thicknesses hd and hm, the residual stress σr, and the width l are chosen so that the line patterns (310) and the underlying walls (211) have random oscillations after etching of the at least one dielectric layer (200, 201, 202).

公开(公告)号：US20210013040A1

公开(公告)日：2021-01-14

申请号：US16926148

申请日：2020-07-10

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS) ,  UNIVERSITE GRENOBLE ALPES

Inventor： Nicolas POSSEME ,  Marceline BONVALOT ,  Ahmad CHAKER ,  Christophe VALLEE

IPC: H01L21/28 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66

Abstract: A method for forming spacers on a gate pattern includes deposition of a first dielectric layer having basal portions on an active layer and side portions of the edges of the pattern; anisotropic modification of only the basal portions of the first layer, so as to obtain modified basal portions; deposition of a second dielectric layer on the first layer, also having basal and side portions; anisotropic etching of only the basal portions of the second layer, so as to remove these basal portions while conserving the side portions; and removal of the modified basal portions while conserving the first and second non-modified side portions, by selective etching of the modified dielectric material vis-à-vis the non-modified dielectric material.

公开(公告)号：US20190278171A1

公开(公告)日：2019-09-12

申请号：US16304933

申请日：2017-05-23

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Raluca TIRON ,  Nicolas POSSEME ,  Xavier CHEVALIER

IPC: G03F7/00 ,  G03F7/004 ,  G03F7/075 ,  G03F7/11

Abstract: A method for forming a functionalised guide pattern for the self-assembly of a block copolymer by graphoepitaxy, includes forming a guide pattern made of a first material having a first chemical affinity for the block copolymer, the guide pattern having a cavity with a bottom and side walls; grafting a functionalisation layer made of a second polymeric material having a second chemical affinity for the block copolymer, the functionalisation layer having a first portion grafted onto the bottom of the cavity and a second portion grafted onto the side walls of the cavity; selectively etching the second portion of the functionalisation layer relative to the first portion of the functionalisation layer, the etching including a step of exposure to an ion beam following a direction that intersects the second portion of the functionalisation layer, such that the ion beam does not reach the first portion of the functionalisation layer.

公开(公告)号：US20190244869A1

公开(公告)日：2019-08-08

申请号：US16230192

申请日：2018-12-21

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Cyrille LE ROYER ,  Yves MORAND

IPC: H01L21/84 ,  C23C16/34 ,  C23C14/06 ,  C23C14/48 ,  C23C28/04 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/223 ,  H01L29/78

CPC classification number: H01L21/84 ,  C23C14/0652 ,  C23C14/48 ,  C23C16/345 ,  C23C28/04 ,  H01L21/02118 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/2236 ,  H01L21/31155 ,  H01L21/823807 ,  H01L29/7843

Abstract: There is provided a method for producing, on one same plate, at least one first transistor surmounted at least partially on a voltage stressed layer and a second transistor surmounted at least partially on a compression stressed layer, the method including providing a plate including the first and the second transistors; forming at least one stressed nitride-based layer, on the first and the second transistors, the layer being voltage stressed; depositing a protective layer so as to cover a first zone of the layer, the first zone covering at least partially the first transistor and leaving a second zone of the layer uncovered, the second zone at least partially covering the second transistor; and modifying a type of stress of the second zone of the layer by implanting hydrogen-based ions from a plasma in the second zone, such that the second zone of the layer is compression stressed.

公开(公告)号：US20180001582A1

公开(公告)日：2018-01-04

申请号：US15538594

申请日：2015-12-22

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Stephan LANDIS ,  Lamia NOURI

IPC: B29D11/00 ,  G03F7/00 ,  G02B3/02 ,  C23C14/04 ,  B81C1/00 ,  C23C14/58 ,  C23C14/48 ,  H01L21/768 ,  G02B3/00

CPC classification number: B29D11/00365 ,  B81B2203/0376 ,  B81C1/00103 ,  B81C1/0046 ,  B81C99/009 ,  B81C2201/0133 ,  B81C2201/0136 ,  C23C14/042 ,  C23C14/48 ,  C23C14/5853 ,  C23C14/5873 ,  G02B3/0025 ,  G02B3/0031 ,  G02B3/02 ,  G03F7/0002 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76817

Abstract: The invention relates in particular to a method for creating patterns in a layer (410) to be etched, starting from a stack comprising at least the layer (410) to be etched and a masking, layer (420) on top of the layer (410) to be etched, the masking layer (420) having at least one pattern (421), the method comprising at least; a) a step of modifying at least one zone (411) of the layer (410) to be etched via ion implantation (430) vertically in line with said at least one pattern (421); b) at least one sequence of steps comprising: b1) a step of enlarging (440) the at least one pattern (421) in a plane in which the layer (410) to be etched mainly extends; b2) a step of modifying at least one zone (411″, 411″) of the layer (410) to be etched via ion implantation (430) vertically in line with the at least one enlarged pattern (421), the implantation being carried out over a depth less than the implantation depth of the preceding, modification step;) c) a step of removing (461, 462) the modified zones (411, 411′, 41″), the removal comprising a step of etching the modified zones (411, 411′, 411″) selectively with respect to the non-modified zones (412) of the layer (410) to be etched.

公开(公告)号：US20170363954A1

公开(公告)日：2017-12-21

申请号：US15538526

申请日：2015-12-22

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Stephan LANDIS ,  Nicolas POSSEME ,  Lamia NOURI

IPC: G03F7/00 ,  B82Y40/00 ,  B82Y10/00

CPC classification number: H01L21/266 ,  B81C1/00103 ,  B81C1/0046 ,  B81C1/00587 ,  B81C2201/0136 ,  B81C2201/0153 ,  B82Y10/00 ,  B82Y40/00 ,  C23C14/042 ,  C23C14/48 ,  G03F7/0002 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L31/02363 ,  H01L31/0392 ,  H01L31/1852 ,  H01L33/007 ,  H01L33/20 ,  H01L33/22 ,  Y02E10/50

Abstract: The invention relates in particular to a method for producing subsequent patterns in an underlying layer (120), the method comprising at least one step of producing prior patterns in a carbon imprintable layer (110) on top of the underlying layer (120), the production of the prior patterns involving nanoimprinting of the imprintable layer (110) and leave in place a continuous layer formed by the imprintable layer (110) and covering the underlying layer (120), characterized in that it comprises the following step: at least one step of modifying the underlying layer (120) via ion implantation (421) in the underlying layer (120), the implantation (421) being carried out through the imprintable layer (110) comprising the subsequent patterns, the parameters of the implantation (421) being chosen in such a way as to form, in the underlying layer (120), implanted zones (122) and non-implanted zones, the non-implanted zones defining the subsequent patterns and having a geometry that is dependent on the prior patterns.