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公开(公告)号：US20120104578A1
公开(公告)日：2012-05-03
申请号：US13342583
申请日：2012-01-03
申请人： Hsien-Pin Hu , Chen-Hu Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
发明人： Hsien-Pin Hu , Chen-Hu Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
IPC分类号： H01L23/495
CPC分类号： H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/97 , H01L25/0655 , H01L2224/05001 , H01L2224/05027 , H01L2224/05571 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/05541 , H01L2224/05005 , H01L2224/05599 , H01L2224/05099
摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.
摘要翻译： 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。 多个管芯结合到插入件晶片的前表面上。 在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。 多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。
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公开(公告)号：US20120040500A1
公开(公告)日：2012-02-16
申请号：US12857245
申请日：2010-08-16
申请人： Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人： Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号： H01L21/56
CPC分类号： H01L21/56 , H01L21/561 , H01L21/565 , H01L21/67126 , H01L23/3121 , H01L24/94 , H01L2224/16145 , H01L2224/81191 , H01L2224/81192 , H01L2224/94 , H01L2924/181 , H01L2224/81 , H01L2924/00
摘要： A system and method for a semiconductor molding chamber is disclosed. An embodiment comprises a top molding portion and a bottom molding portion that form a cavity between them into which a semiconductor wafer is placed. The semiconductor molding chamber has a first set of vacuum tubes which hold and fix the position of the semiconductor wafer and a second set of vacuum tubes which evacuate the cavity of extraneous ambient gasses. The encapsulant may then be placed over the semiconductor wafer in order to encapsulate the semiconductor wafer.
摘要翻译： 公开了一种用于半导体模制室的系统和方法。 一个实施例包括顶部模制部分和底部模制部分，其在其间放置半导体晶片的它们之间形成空腔。 半导体模制室具有第一组真空管，其保持和固定半导体晶片的位置，以及第二组真空管，其抽空外部环境气体的空腔。 然后可以将密封剂放置在半导体晶片上以便封装半导体晶片。
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公开(公告)号：US20110278732A1
公开(公告)日：2011-11-17
申请号：US12779734
申请日：2010-05-13
申请人： Chen-Hua Yu , Wen-Chih Chiou , Shin-Puu Jeng , Tsang-Jiuh Wu
发明人： Chen-Hua Yu , Wen-Chih Chiou , Shin-Puu Jeng , Tsang-Jiuh Wu
IPC分类号： H01L23/522 , H01L21/50
CPC分类号： H01L21/76895 , H01L21/563 , H01L21/76883 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L23/5283 , H01L25/0657 , H01L25/18 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2225/06517 , H01L2225/06548 , H01L2225/06572 , H01L2225/06589 , H01L2924/01019 , H01L2924/01025 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/15311 , H01L2924/00
摘要： A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like.
摘要翻译： 提供了一种与集成电路一起使用的装置。 该器件包括具有通过其形成的贯通基板通孔的基板。 电介质层形成在衬底的至少一侧上，并且在电介质层内形成金属化层。 最靠近贯穿衬底通孔的第一金属化层大于一个或多个上覆的金属化层。 在一个实施例中，顶部金属化层大于一个或多个下面的金属化层。 集成电路管芯可以在衬底的一侧或两侧附着到衬底，并且衬底的任一侧可以附接到另一衬底，例如印刷电路板，高密度互连，封装衬底，有机 基板，层叠基板等。
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公开(公告)号：US08765549B2
公开(公告)日：2014-07-01
申请号：US13458476
申请日：2012-04-27
申请人： Chun Hua Chang , Shin-Puu Jeng , Der-Chyang Yeh , Shang-Yun Hou , Wen-Chih Chiou
发明人： Chun Hua Chang , Shin-Puu Jeng , Der-Chyang Yeh , Shang-Yun Hou , Wen-Chih Chiou
IPC分类号： H01L21/8242
CPC分类号： H01L23/642 , H01L23/49822 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate.
摘要翻译： 公开了用于衬底的电容器设计，例如插入件及其制造方法。 在一个实施例中，在通孔和下层金属化层之间形成电容器。 电容器可以是例如形成在衬底上或形成在衬底上的电介质层上的平面电容器。
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公开(公告)号：US08749027B2
公开(公告)日：2014-06-10
申请号：US12349901
申请日：2009-01-07
申请人： Hsien-Wei Chen , Shin-Puu Jeng , Hung-Jung Tu , Wen-Chih Chiou
发明人： Hsien-Wei Chen , Shin-Puu Jeng , Hung-Jung Tu , Wen-Chih Chiou
IPC分类号： H01L23/544 , H01L29/40
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/585 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/15311
摘要： A die includes a seal-ring structure below a substrate. The seal-ring structure is disposed around at least one substrate region. At least one means for substantially preventing ion diffusion into the substrate region. The at least one means is coupled with the seal-ring structure.
摘要翻译： 模具包括在基底下方的密封环结构。 密封环结构围绕至少一个基底区域设置。 至少一种用于基本上防止离子扩散进入衬底区域的装置。 至少一个装置与密封环结构联接。
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公开(公告)号：US08716867B2
公开(公告)日：2014-05-06
申请号：US12778867
申请日：2010-05-12
申请人： Francis Ko , Chi-Chun Hsieh , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人： Francis Ko , Chi-Chun Hsieh , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号： B41F33/00
CPC分类号： H01L23/5384 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/49883 , H01L23/525 , H01L23/5328 , H01L24/05 , H01L24/13 , H01L24/14 , H01L2224/0401 , H01L2224/05572 , H01L2224/13009 , H01L2224/13147 , H01L2224/13644 , H01L2224/13655 , H01L2224/14181 , H01L2924/00014 , H01L2924/0002 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.
摘要翻译： 形成器件的方法包括在电介质片上印刷导电图案以形成预先印墨的片材，以及将预印墨片材粘合到基片的一侧上。 导电特征包括从衬底的第一主侧延伸到与第一主侧相对的衬底的第二主侧的贯通衬底。 然后施加导电膏以将导电图案电耦合到衬底中的导电特征。
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公开(公告)号：US08674513B2
公开(公告)日：2014-03-18
申请号：US12779734
申请日：2010-05-13
申请人： Chen-Hua Yu , Wen-Chih Chiou , Shin-Puu Jeng , Tsang-Jiuh Wu
发明人： Chen-Hua Yu , Wen-Chih Chiou , Shin-Puu Jeng , Tsang-Jiuh Wu
IPC分类号： H01L23/522
CPC分类号： H01L21/76895 , H01L21/563 , H01L21/76883 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L23/5283 , H01L25/0657 , H01L25/18 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2225/06517 , H01L2225/06548 , H01L2225/06572 , H01L2225/06589 , H01L2924/01019 , H01L2924/01025 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/15311 , H01L2924/00
摘要： A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like.
摘要翻译： 提供了一种与集成电路一起使用的装置。 该器件包括具有通过其形成的贯通基板通孔的基板。 电介质层形成在衬底的至少一侧上，并且在电介质层内形成金属化层。 最靠近贯穿衬底通孔的第一金属化层大于一个或多个上覆的金属化层。 在一个实施例中，顶部金属化层大于一个或多个下面的金属化层。 集成电路管芯可以在衬底的一侧或两侧附着到衬底，并且衬底的任一侧可以附接到另一个衬底，例如印刷电路板，高密度互连，封装衬底，有机 基板，层叠基板等。
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公开(公告)号：US20130285200A1
公开(公告)日：2013-10-31
申请号：US13458476
申请日：2012-04-27
申请人： Chun Hua Chang , Shin-Puu Jeng , Der-Chyang Yeh , Shang-Yun Hou , Wen-Chih Chiou
发明人： Chun Hua Chang , Shin-Puu Jeng , Der-Chyang Yeh , Shang-Yun Hou , Wen-Chih Chiou
CPC分类号： H01L23/642 , H01L23/49822 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate.
摘要翻译： 公开了用于衬底的电容器设计，例如插入件及其制造方法。 在一个实施例中，在通孔和下层金属化层之间形成电容器。 电容器可以是例如形成在衬底上或形成在衬底上的电介质层上的平面电容器。
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公开(公告)号：US20100171203A1
公开(公告)日：2010-07-08
申请号：US12349901
申请日：2009-01-07
申请人： Hsien-Wei CHEN , Shin-Puu Jeng , Hung-Jung Tu , Wen-Chih Chiou
发明人： Hsien-Wei CHEN , Shin-Puu Jeng , Hung-Jung Tu , Wen-Chih Chiou
IPC分类号： H01L25/065 , H01L23/48
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/585 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/15311
摘要： A die includes a seal-ring structure below a substrate. The seal-ring structure is disposed around at least one substrate region. At least one means for substantially preventing ion diffusion into the substrate region. The at least one means is coupled with the seal-ring structure.
摘要翻译： 模具包括在基底下方的密封环结构。 密封环结构围绕至少一个基底区域设置。 至少一种用于基本上防止离子扩散进入衬底区域的装置。 至少一个装置与密封环结构联接。
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公开(公告)号：US08878338B2
公开(公告)日：2014-11-04
申请号：US13485340
申请日：2012-05-31
申请人： Chun Hua Chang , Der-Chyang Yeh , Kuang-Wei Cheng , Yuan-Hung Liu , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng
发明人： Chun Hua Chang , Der-Chyang Yeh , Kuang-Wei Cheng , Yuan-Hung Liu , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng
CPC分类号： H01L28/40 , H01L21/02 , H01L21/768 , H01L23/147 , H01L23/49822 , H01L23/49827 , H01L23/50 , H01L23/5223 , H01L23/53295 , H01L28/60 , H01L29/02 , H01L2924/0002 , H01L2924/00
摘要： Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. A through via is formed in the interposer, and a capacitor is formed between a lower level metallization layer and a higher level metallization layer. The capacitor may be, for example, a planar capacitor with dual capacitor dielectric layers.
摘要翻译： 公开了用于衬底的电容器设计，例如插入件及其制造方法。 在插入器中形成通孔，并且在下层金属化层和较高级金属化层之间形成电容器。 电容器可以是例如具有双电容器电介质层的平面电容器。
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