公开(公告)号：US09706656B2

公开(公告)日：2017-07-11

申请号：US14950584

申请日：2015-11-24

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chien-Min Hsu ,  Shih-Hsien Wu ,  Jing-Yao Chang ,  Tao-Chih Chang ,  Ren-Shin Cheng ,  Min-Lin Lee

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42

CPC classification number: H05K1/116 ,  H05K1/0251 ,  H05K3/42 ,  H05K2201/0187 ,  H05K2201/09545 ,  H05K2203/1105 ,  H05K2203/1178 ,  H05K2203/143 ,  H05K2203/1438

Abstract: A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.

公开(公告)号：US20170104027A1

公开(公告)日：2017-04-13

申请号：US14979533

申请日：2015-12-28

Applicant: Industrial Technology Research Institute

Inventor： Wei-Chung Lo ,  Yu-Wei Huang ,  Tao-Chih Chang ,  Chih-Ming Shen

IPC: H01L27/15 ,  H01L33/00 ,  H01L33/62 ,  H01L33/38

CPC classification number: H01L27/156 ,  H01L25/0753 ,  H01L33/005 ,  H01L33/38 ,  H01L33/62 ,  H01L2224/48139 ,  H01L2933/0016 ,  H01L2933/0066

Abstract: In an embodiment, a light emitting device comprises a light emitting diode chip and a spherical extending electrode. The light emitting diode chip includes a semiconductor epitaxial structure, a first electrode and a second electrode. The first electrode and the second electrode are disposed on two opposite sides of the semiconductor epitaxial structure, respectively. The first electrode is disposed between the semiconductor epitaxial structure and the spherical extending electrode, and the spherical extending electrode is electrically connected to the semiconductor epitaxial structure electrically through the first electrode. The volume of the spherical extending electrode is greater than that of the light emitting diode chip.

公开(公告)号：US20140374629A1

公开(公告)日：2014-12-25

申请号：US14018434

申请日：2013-09-05

Applicant: Industrial Technology Research Institute

Inventor： Shin-Yi Huang ,  Wen-Chih Chen ,  Tao-Chih Chang

IPC: H04B10/80

CPC classification number: H04B10/802 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40137 ,  H01L2224/40225 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/13055 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A power module for high/low voltage insulation is provided. The power module includes a first substrate, a second substrate and an insulating substrate. The first substrate includes a first control circuit and a light source, wherein the first control circuit controls the light source to emit light. The second substrate includes a light-sensing part, a second control circuit and a power device. The light-sensing part receives the light of the light source of the first substrate to send a sensing information. The second control circuit correspondingly drives the power device in accordance with the sensing information. The insulating substrate is disposed between the first substrate and second substrate.

Abstract translation: 提供高/低压绝缘电源模块。 功率模块包括第一衬底，第二衬底和绝缘衬底。 第一基板包括第一控制电路和光源，其中第一控制电路控制光源发光。 第二基板包括光感测部件，第二控制电路和功率器件。 光检测部分接收第一基板的光源的光以发送感测信息。 第二控制电路根据感测信息相应地驱动功率器件。 绝缘基板设置在第一基板和第二基板之间。

公开(公告)号：US20140134459A1

公开(公告)日：2014-05-15

申请号：US13855719

申请日：2013-04-03

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen

IPC: B23K35/24 ,  B32B15/01

CPC classification number: B23K35/24 ,  B23K35/282 ,  B23K35/3013 ,  B23K35/302 ,  B32B15/01 ,  B32B15/018 ,  H01L23/3735 ,  H01L23/49513 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/04026 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/2612 ,  H01L2224/27826 ,  H01L2224/291 ,  H01L2224/29118 ,  H01L2224/29561 ,  H01L2224/29565 ,  H01L2224/29582 ,  H01L2224/29583 ,  H01L2224/29639 ,  H01L2224/29644 ,  H01L2224/29647 ,  H01L2224/29663 ,  H01L2224/29664 ,  H01L2224/29669 ,  H01L2224/29673 ,  H01L2224/29676 ,  H01L2224/29678 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/83007 ,  H01L2224/8309 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83815 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/15787 ,  Y10T428/12792 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01076 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A solder and a solder joint structure formed by the solder are provided. The solder includes a zinc-based material, a copper film, and a noble metal film. The copper film completely covers the surface of the zinc-based material. The noble metal film completely covers the copper film. The solder joint structure includes a zinc-based material and an intermetallic layer. The intermetallic layer consists of zinc and noble metal and completely covers the surface of the zinc-based material.

Abstract translation: 提供由焊料形成的焊料和焊点结构。 焊料包括锌基材料，铜膜和贵金属膜。 铜膜完全覆盖锌基材料的表面。 贵金属膜完全覆盖铜膜。 焊接结构包括锌基材料和金属间化合物层。 金属间层由锌和贵金属组成，并完全覆盖锌基材料的表面。

公开(公告)号：US20130168798A1

公开(公告)日：2013-07-04

申请号：US13727599

申请日：2012-12-27

Applicant: Industrial Technology Research Institute

Inventor： Jing-Yao Chang ,  Tao-Chih Chang ,  Yu-Wei Huang ,  Yu-Min Lin ,  Shin-Yi Huang

IPC: H01L25/16

CPC classification number: H01L25/16 ,  H01L23/3121 ,  H01L23/38 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/157 ,  H01L2924/15786 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A first back surface of a first chip faces toward a carrier. A first active surface of the first chip has first pads and a first insulting layer thereon. A second chip is disposed on the first chip and electrically connected to the carrier. A second active surface of the second chip faces toward the first active surface. The second active surface has second pads and a second insulting layer thereon. Bumps connect the first and second pads. First and second daisy chain circuits are respectively disposed on the first and second insulting layers. Hetero thermoelectric device pairs are disposed between the first and second chips and connected in series by the first and second daisy chain circuits, and constitute a circuit with an external device. First and second heat sinks are respectively disposed on a second surface of the carrier and a second back surface of the second chip.

Abstract translation: 第一芯片的第一后表面朝向载体。 第一芯片的第一有源表面具有第一焊盘和其上的第一绝缘层。 第二芯片设置在第一芯片上并电连接到载体。 第二芯片的第二有源表面朝向第一有源表面。 第二活性表面在其上具有第二垫和第二绝缘层。 碰撞连接第一和第二垫。 第一和第二菊花链电路分别设置在第一和第二绝缘层上。 异质热电元件对设置在第一和第二芯片之间并且由第一和第二菊花链电路串联连接，并且构成具有外部装置的电路。 第一和第二散热器分别设置在载体的第二表面和第二芯片的第二后表面上。

公开(公告)号：US11756858B2

公开(公告)日：2023-09-12

申请号：US17140145

申请日：2021-01-04

Applicant: Industrial Technology Research Institute ,  DIODES TAIWAN S.A R.L.

Inventor： Wei-Kuo Han ,  Chia-Yen Lee ,  Jing-Yao Chang ,  Tao-Chih Chang

IPC: H01L23/40

CPC classification number: H01L23/40

Abstract: A power module including a main housing, a power element, and at least one assembling component is provided. The main housing has at least one side wall and at least two ribs extending from the side wall. The power element is disposed in the main housing and is closely pressed against a heat dissipation structure by the side wall. The assembling component includes a main section and two bending sections. The main section is located between the two ribs and includes a central portion, at least one movable component, and a peripheral portion. The central portion has a fastening portion, the peripheral portion surrounds the central portion, and the movable component is connected between the central portion and the peripheral portion. The two bending sections are respectively connected to two opposite sides of the peripheral portion and are respectively embedded in the two ribs.

公开(公告)号：US11114387B2

公开(公告)日：2021-09-07

申请号：US16108272

申请日：2018-08-22

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Jing-Yao Chang ,  Tao-Chih Chang ,  Fang-Jun Leu ,  Wei-Kuo Han ,  Kuo-Shu Kao

IPC: H01L23/00

Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material. A maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is greater than the thickness of the intermetallic compound disposed between the electronic device and the conductive layer.

公开(公告)号：US20210210409A1

公开(公告)日：2021-07-08

申请号：US17140145

申请日：2021-01-04

Applicant: Industrial Technology Research Institute ,  Lite-On Semiconductor Corporation

Inventor： Wei-Kuo Han ,  Chia-Yen Lee ,  Jing-Yao Chang ,  Tao-Chih Chang

IPC: H01L23/40

Abstract: A power module including a main housing, a power element, and at least one assembling component is provided. The main housing has at least one side wall and at least two ribs extending from the side wall. The power element is disposed in the main housing and is closely pressed against a heat dissipation structure by the side wall. The assembling component includes a main section and two bending sections. The main section is located between the two ribs and includes a central portion, at least one movable component, and a peripheral portion. The central portion has a fastening portion, the peripheral portion surrounds the central portion, and the movable component is connected between the central portion and the peripheral portion. The two bending sections are respectively connected to two opposite sides of the peripheral portion and are respectively embedded in the two ribs.

公开(公告)号：US10784297B2

公开(公告)日：2020-09-22

申请号：US16194802

申请日：2018-11-19

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Tao-Chih Chang

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/31

Abstract: A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip.

公开(公告)号：US20200083332A1

公开(公告)日：2020-03-12

申请号：US16561023

申请日：2019-09-05

Applicant: Industrial Technology Research Institute

Inventor： Heng Lee ,  Shin-Yi Huang ,  Tao-Chih Chang

IPC: H01L29/24 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/51

Abstract: A semiconductor device includes a substrate, a channel layer, a first electrode layer, a second electrode layer, and a gate structure. The substrate includes a first gallium oxide layer. The channel layer is disposed on the substrate, where the channel layer is a second gallium oxide layer. The first electrode layer and the second electrode layer are disposed on the channel layer. The gate structure is disposed on the channel layer between the first electrode layer and the second electrode layer. The gate structure is on the channel layer or the gate structure has a bottom portion extending into the channel layer.