公开(公告)号：US20200006138A1

公开(公告)日：2020-01-02

申请号：US16024692

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Sudipto NASKAR ,  Manish CHANDHOK ,  Miriam RESHOTKO ,  Rami HOURANI

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

公开(公告)号：US20190146335A1

公开(公告)日：2019-05-16

申请号：US16097960

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： James M. BLACKWELL ,  Robert L. BRISTOL ,  Marie KRYSAK ,  Florian GSTREIN ,  Eungnak HAN ,  Kevin L. LIN ,  Rami HOURANI ,  Shane M. HARLSON

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/768 ,  G03F7/40

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

公开(公告)号：US20190139887A1

公开(公告)日：2019-05-09

申请号：US16096272

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Richard E. SCHENKER ,  Jeffery D. BIELEFELD ,  Rami HOURANI ,  Manish CHANDHOK

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.

公开(公告)号：US20170345643A1

公开(公告)日：2017-11-30

申请号：US15529482

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Todd R. YOUNKIN ,  Michael J. LEESON ,  James M. BLACKWELL ,  Ernisse S. PUTNA ,  Marie KRYSAK ,  Rami HOURANI ,  Eungnak HAN ,  Robert L. BRISTOL

IPC: H01L21/027 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/0271 ,  G03F7/0035 ,  G03F7/094 ,  G03F7/095 ,  G03F7/115 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/528 ,  H01L2224/16225

Abstract: Photodefinable alignment layers for chemical assisted patterning and approaches for forming photodefinable alignment layers for chemical assisted patterning are described. An embodiment of the invention may include disposing a chemically amplified resist (CAR) material over a hardmask that includes a switch component. The CAR material may then be exposed to form exposed resist portions. The exposure may produces acid in the exposed portions of the CAR material that interact with the switch component to form modified regions of the hardmask material below the exposed resist portions.

公开(公告)号：US20240088143A1

公开(公告)日：2024-03-14

申请号：US18516595

申请日：2023-11-21

Applicant: Intel Corporation

Inventor： Szuya S. Liao ,  Scott B. CLENDENNING ,  Jessica TORRES ,  Lukas BAUMGARTEL ,  Kiran CHIKKADI ,  Diane LANCASTER ,  Matthew V. METZ ,  Florian GSTREIN ,  Martin M. MITAN ,  Rami HOURANI

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/538 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/5384 ,  H01L23/5389 ,  H01L27/0924 ,  H01L21/823462 ,  H01L21/823871

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：US20220238376A1

公开(公告)日：2022-07-28

申请号：US17720152

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Sudipto NASKAR ,  Manish CHANDHOK ,  Miriam RESHOTKO ,  Rami HOURANI

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

公开(公告)号：US20190318958A1

公开(公告)日：2019-10-17

申请号：US16317015

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Kevin L. LIN ,  James M. BLACKWELL ,  Rami HOURANI ,  Eungnak HAN

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on photobucket floor colors with selective grafting for semiconductor structure fabrication, and the resulting structures, are described. For example, a grating structure is formed above an ILD layer formed above a substrate, the grating structure including a plurality of dielectric spacers separated by alternating first trenches and second trenches, grafting a resist-inhibitor layer in the first trenches but not in the second trenches, forming photoresist in the first trenches and in the second trenches, exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations, etching the set of via locations into the ILD layer, and forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.

公开(公告)号：US20190267282A1

公开(公告)日：2019-08-29

申请号：US16346256

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Florian GSTREIN ,  Rami HOURANI ,  Gopinath BHIMARASETTI ,  James M. BLACKWELL

IPC: H01L21/768 ,  H01L21/308 ,  H01L23/528

Abstract: Bottom-up fill dielectric materials for semiconductor structure fabrication, and methods of fabricating bottom-up fill dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a dielectric material for semiconductor structure fabrication includes forming a trench in a material layer above a substrate. A blocking layer is formed partially into the trench along upper portions of sidewalls of the trench. A dielectric layer is formed filling a bottom portion of the trench with a dielectric material up to the blocking layer. The blocking layer is removed. The forming the blocking layer, the forming the dielectric layer, and the removing the blocking layer are repeated until the trench is completely filled with the dielectric material.

公开(公告)号：US20190189803A1

公开(公告)日：2019-06-20

申请号：US16271226

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Grant KLOSTER ,  Scott B. CLENDENNING ,  Rami HOURANI ,  Szuya S. LIAO ,  Patricio E. ROMERO ,  Florian GSTREIN

IPC: H01L29/78 ,  H01L21/32 ,  H01L21/3105 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L29/7851 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31133 ,  H01L21/32 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42368 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696

Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.

公开(公告)号：US20180122690A1

公开(公告)日：2018-05-03

申请号：US15573457

申请日：2015-06-22

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/02

CPC classification number: H01L21/76816 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/0335 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76897 ,  H01L2224/16225

Abstract: Image tone-reversal with a dielectric using bottom-up cross-linking for back end of line (BEOL) interconnects is described. In an example, a semiconductor structure including a metallization layer includes a plurality of trenches in an interlayer dielectric (ILD) layer above a substrate. A pre-catalyst layer is on sidewalls of one or more, but not all, of the plurality of trenches. Cross-linked portions of a dielectric material are proximate the pre-catalyst layer, in the one or more of the plurality of trenches. Conductive structures are in remaining ones of the trenches.