公开(公告)号：US12159813B2

公开(公告)日：2024-12-03

申请号：US18111329

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Aditya S. Vaidya ,  Ravindranath V. Mahajan ,  Digvijay A. Raorane ,  Paul R. Start

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/49 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the bridge die. The bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US11832419B2

公开(公告)日：2023-11-28

申请号：US16723865

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  Nicholas S. Haehn ,  Je-Young Chang ,  Kyle Arrington ,  Aaron McCann ,  Edvin Cetegen ,  Ravindranath V. Mahajan ,  Robert L. Sankman ,  Ken P. Hackenberg ,  Sergio A. Chan Arguedas

IPC: H05K7/20 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

CPC classification number: H05K7/20309 ,  H01L23/3672 ,  H01L23/49816 ,  H01L24/14

Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.

公开(公告)号：US11756889B2

公开(公告)日：2023-09-12

申请号：US16534027

申请日：2019-08-07

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Kevin McCarthy ,  Leigh M. Tribolet ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Robert L. Sankman

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/20 ,  H01L24/80 ,  H01L2221/68354 ,  H01L2221/68372 ,  H01L2224/08225 ,  H01L2224/214 ,  H01L2224/80006 ,  H01L2224/80894 ,  H01L2924/0105 ,  H01L2924/01029 ,  H01L2924/05442

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.

公开(公告)号：US11664293B2

公开(公告)日：2023-05-30

申请号：US16665621

申请日：2019-10-28

Applicant: Intel Corporation

Inventor： Krishna Vasanth Valavala ,  Ravindranath V. Mahajan ,  Chandra Mohan Jha

IPC: H01L23/38 ,  H01L23/42 ,  H01L23/367 ,  H01L23/10 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/38 ,  H01L21/4871 ,  H01L23/10 ,  H01L23/367 ,  H01L23/42 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16225

Abstract: Embodiments include a semiconductor package with a thermoelectric cooler (TEC), a method to form such semiconductor package, and a semiconductor packaged system. The semiconductor package includes a die with a plurality of backend layers on a package substrate. The backend layers couple the die to the package substrate. The semiconductor package includes the TEC in the backend layers of the die. The TEC includes a plurality of N-type layers, a plurality of P-type layers, and first and second conductive layers. The first conductive layer is directly coupled to outer regions of bottom surfaces of the N-type and P-type layers, and the second conductive layer is directly coupled to inner regions of top surfaces of the N-type and P-type layers. The first conductive layer has a width greater than a width of the second conductive layer. The N-type and P-type layers are directly disposed between the first and second conductive layers.

公开(公告)号：US11569173B2

公开(公告)日：2023-01-31

申请号：US15857752

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Andrew P. Collins ,  Digvijay A. Raorane ,  Wilfred Gomes ,  Ravindranath V. Mahajan ,  Sujit Sharan

IPC: H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48 ,  H01L21/50 ,  H01L25/18

Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.

公开(公告)号：US11328968B2

公开(公告)日：2022-05-10

申请号：US16463638

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Mitul Modi ,  Robert L. Sankman ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Amruthavalli P. Alur ,  Yikang Deng ,  Eric J. Li

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

公开(公告)号：US10468331B2

公开(公告)日：2019-11-05

申请号：US15869700

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Je-young Chang ,  Jae W. Kim ,  Ravindranath V. Mahajan ,  Blake Rogers ,  Devdatta Kulkarni

IPC: H01L23/48 ,  H01L23/473 ,  F28D9/00 ,  B23P15/26 ,  F28D21/00 ,  H01L23/28 ,  H01L23/00 ,  G06F1/20

Abstract: A heat management system may include a die package. The die package may include a housing. The housing may include a housing surface. The housing may include a housing inlet port. The housing inlet port may be in communication with the housing surface. The housing may include a housing outlet port. The housing outlet port may be in communication with the housing surface.The heat management system may include a manifold. The manifold may be configured to couple with the housing. The manifold may include a manifold surface. The manifold surface may be configured to mate with the housing surface. The manifold may include a manifold inlet port. The manifold inlet port may be in communication with the manifold surface. The manifold may include a manifold outlet port. The manifold outlet port may be in communication with the manifold surface.

公开(公告)号：US20190326198A1

公开(公告)日：2019-10-24

申请号：US16457336

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Aditya S. Vaidya ,  Ravindranath V. Mahajan ,  Digvijay A. Raorane ,  Paul R. Start

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/16 ,  H01L21/768 ,  H01L23/498

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US20180366438A1

公开(公告)日：2018-12-20

申请号：US15781998

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Sujit Sharan ,  Ravindranath V. Mahajan

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00

Abstract: A package assembly includes a substrate extending from a first substrate end to a second substrate end. A plurality of conductive traces extend along the substrate. A plurality of contacts are coupled with the respective conductive traces of the plurality of conductive traces. Each of the contacts of the plurality of contacts includes a contact pad coupled with a respective conductive trace of the plurality of conductive traces, and a contact post coupled with the contact pad, the contact post extends from the contact pad. A package cover layer is coupled over the plurality of contact posts. The plurality of contact posts are configured to penetrate the package cover layer and extend to a raised location above the package cover layer.

公开(公告)号：US20180263117A1

公开(公告)日：2018-09-13

申请号：US15810800

申请日：2017-11-13

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Robert L. Sankman ,  Charles Gealer ,  Omkar Karhade ,  John S. Guzek ,  Ravindranath V. Mahajan ,  James C. Matayabas, JR. ,  Johanna M. Swan ,  Feras Eid ,  Shawna Liff ,  Timothy McIntosh ,  Telesphor Kamgaing ,  Adel A. Elsherbini ,  Kemal Aygun

IPC: H05K1/18 ,  H01L23/00

CPC classification number: H05K1/189 ,  G06F1/163 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H05K1/0393 ,  H05K1/181 ,  H05K1/185 ,  H05K13/0469 ,  H05K2201/0137 ,  H05K2203/1469 ,  Y10T29/49146 ,  H01L2924/00

Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.