-
公开(公告)号：US20170126249A1
公开(公告)日：2017-05-04
申请号：US14929163
申请日：2015-10-30
Applicant: INTEL CORPORATION
Inventor： Wei WU , Charles AUGUSTINE , Shigeki TOMISHIMA , Shih-lien L. LU , James W. TSCHANZ
CPC classification number: H03M13/05 , G06F11/1048 , H03M13/1515 , H03M13/353 , H03M13/611 , H03M13/6502 , H03M13/6516
Abstract: In one embodiment, temperature dependent, multiple mode error correction in accordance with one aspect of this disclosure, is employed for a memory circuit containing arrays of memory cells. In one embodiment, a temperature sensor coupled to an array is configured to provide an output signal which is a function of the temperature of the array of memory cells. Multiple mode error correction code (ECC) logic having an input coupled to an output of the temperature sensor, is configured to encode write data and decode read data for the array of memory cells in an error correction code in one of a plurality of error correction modes as a function of the temperature of the array of memory cells. Other aspects are described herein.
-
公开(公告)号：US20160188890A1
公开(公告)日：2016-06-30
申请号：US14583513
申请日：2014-12-26
Applicant: INTEL CORPORATION
Inventor： Helia NAEIMI , Shigeki TOMISHIMA , Shih-Lien L. LU
CPC classification number: G06F21/62 , G06F12/0246 , G06F12/1433 , G06F21/34 , G06F21/74 , G06F21/77 , G06F21/79 , G06F2212/1052 , G06F2212/7201 , G06F2212/7205 , G06F2221/2143 , H04W12/1206
Abstract: In one embodiment, a device containing sensitive information may be placed in a data security mode. In such a data security mode, certain activities may trigger the partial or full erasure of the sensitive date before the data can be retrieved by an unauthorized user. In one embodiment, the data security mode may be a “park” mode in which unauthorized physical movement of the device triggers the partial or full erasure of the sensitive data stored in a nonvolatile memory before the data can be retrieved by an unauthorized user. In another aspect of the present description, the earth's magnetic field may be used to detect movement of a device in the park mode, and may be used to power the erasure of sensitive data as the device is moved relative to the earth's magnetic field. Other aspects are described herein.
Abstract translation: 在一个实施例中，可以将包含敏感信息的设备置于数据安全模式中。 在这样的数据安全模式中，某些活动可能会触发敏感日期的部分或全部擦除，然后才能由未经授权的用户检索数据。 在一个实施例中，数据安全模式可以是“驻留”模式，其中在未经授权的用户可以检索数据之前，设备的未经授权的物理移动触发存储在非易失性存储器中的敏感数据的部分或全部擦除。 在本说明书的另一方面，地球磁场可用于检测驻留模式中的装置的移动，并且可以用于在设备相对于地球磁场移动时对敏感数据的擦除提供动力。 本文描述了其它方面。
-
公开(公告)号：US20160188495A1
公开(公告)日：2016-06-30
申请号：US14583518
申请日：2014-12-26
Applicant: INTEL CORPORATION
Inventor： Helia NAEIMI , Shigeki TOMISHIMA , Shih-Lien L. LU
CPC classification number: G06F12/1425 , G06F12/0246 , G06F21/79 , G06F2212/1052 , G06F2212/7205 , G06F2212/7209 , G06F2221/2143 , G11C5/148 , G11C7/24 , G11C11/161 , G11C11/1675 , G11C11/1695 , G11C11/1697 , G11C14/0081 , G11C16/105 , G11C16/107 , G11C16/14 , G11C16/16 , G11C16/22 , G11C16/3486
Abstract: One aspect of the present description provides for automatically erasing at least a portion of a memory such as a nonvolatile memory, for example, of a device in response to a detected event such as a power shutdown or power-up process, for example. In one embodiment, an on-board erasure assistance device such as an electro-magnet, for example, facilitates sensitive data erasure. In accordance with another aspect of the present description, a satisfactory level of sensitive data erasure may be achieved by resetting a portion of the bits of the sensitive data, instead of resetting all the bits of sensitive data. In one embodiment, the bits which are reset to erase sensitive data may be randomly distributed over a subarray. Other aspects are described herein.
Abstract translation: 本说明书的一个方面提供了例如响应于检测到的事件（例如电源关闭或上电过程）来自动擦除诸如设备的非易失性存储器的存储器的至少一部分。 在一个实施例中，诸如电磁体的车载擦除辅助装置例如有利于敏感的数据擦除。 根据本说明书的另一方面，可以通过复位敏感数据的位的一部分而不是重置敏感数据的所有位来实现令人满意的敏感数据擦除级别。 在一个实施例中，复位以擦除敏感数据的位可以随机分布在子阵列上。 本文描述了其它方面。
-
公开(公告)号：US20240404617A1
公开(公告)日：2024-12-05
申请号：US18805118
申请日：2024-08-14
Applicant: Intel Corporation
Inventor： Kuljit S. BAINS , Shigeki TOMISHIMA
Abstract: A system enables an alert signal test mode. The system has an alert signal line between the memory device and the memory controller. The memory device has a register that controls entry into the alert signal test mode. The memory controller sends a command to trigger the memory device to enter the alert signal test mode. In response to the commands, the memory device asserts the alert signal line with an alert signal in response to entry into the alert signal test mode.
-
公开(公告)号：US20240134982A1
公开(公告)日：2024-04-25
申请号：US18401428
申请日：2023-12-30
Applicant: Intel Corporation
Inventor： George VERGIS , Shigeki TOMISHIMA
CPC classification number: G06F21/566 , G06F21/554 , G06F2221/034
Abstract: Examples include techniques for a memory module per row activate counter. The techniques include detecting a row hammer or row disturb condition for a row address at a volatile memory device if an activate count to the row address matches a threshold count. The activate count is maintained by a controller for the memory module. Detection of the row hammer or row disturb condition can cause refresh management actions to mitigate the row hammer or row disturb condition.
-
Patent Agency Ranking
26.发明申请公开(公告)号：US20200311019A1
公开(公告)日：2020-10-01
申请号：US16737779
申请日：2020-01-08
Applicant: Intel Corporation
Inventor： Shigeki TOMISHIMA , Srikanth SRINIVASAN , Chetan CHAUHAN , Rajesh SUNDARAM , Jawad B. KHAN
Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.
-
公开(公告)号：US20180181344A1
公开(公告)日：2018-06-28
申请号：US15391684
申请日：2016-12-27
Applicant: Intel Corporation
Inventor： Shigeki TOMISHIMA , Kuljit S. BAINS
IPC: G06F3/06
Abstract: A programmable data pattern for repeated writes to memory can enable efficient writing of a data pattern to multiple memory locations without transmitting the data pattern for each write. In one embodiment, a memory device includes input/output (I/O) circuitry to receive a command, a register to store a value to indicate a source of a data pattern to write in response to receipt of the command, and access circuitry to, in response to receipt of the command, write the data pattern to memory based on the source indicated by the value in the register.
-
公开(公告)号：US20180025764A1
公开(公告)日：2018-01-25
申请号：US15676964
申请日：2017-08-14
Applicant: INTEL CORPORATION
Inventor： Helia NAEIMI , Shih-Lien L. LU , Shigeki TOMISHIMA
IPC: G11C11/16
CPC classification number: G11C11/1675 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1673
Abstract: In one embodiment, a magnetoresistance random access memory (MRAM) such as a spin transfer torque (STT) random access memory (RAM), for example, has a subarray of bitcells and an electro-magnet positioned adjacent the subarray. A magnetic field is directed through a ferromagnetic device of bitcells of the first subarray to assist in the changing of states of bitcells of the subarray from a first state to a second state in which the ferromagnetic device of the bitcell is changed from one of parallel and anti-parallel polarization to the other of parallel and anti-parallel polarization. Accordingly, the content of the subarray may be readily preset or erased to one of the parallel or anti-parallel state with assistance from an electro-magnet. During a normal write operation, the bits to the other state are written. Other aspects are described herein.
-
公开(公告)号：US20170178697A1
公开(公告)日：2017-06-22
申请号：US14975298
申请日：2015-12-18
Applicant: INTEL CORPORATION
Inventor： Wei WU , Shigeki TOMISHIMA , Shih-Lien L. LU
CPC classification number: G11C7/06 , G06F13/1678 , G06F13/4018 , G06F13/4282 , G11C7/1048 , G11C7/1072 , G11C11/40618 , G11C11/4091 , G11C11/4093 , G11C2207/105 , G11C2207/107
Abstract: Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.
-
公开(公告)号：US20170177526A1
公开(公告)日：2017-06-22
申请号：US14975305
申请日：2015-12-18
Applicant: INTEL CORPORATION
Inventor： Wei WU , Shigeki TOMISHIMA , Shih-Lien L. LU
IPC: G06F13/40 , G11C11/4093 , G06F13/16 , G11C11/4091
CPC classification number: G06F13/4022 , G06F13/1668 , G11C5/025 , G11C5/063 , G11C7/06 , G11C7/1048 , G11C11/4091 , G11C11/4093 , G11C2207/105 , G11C2207/107
Abstract: Provided are a memory device and a memory bank comprised of a local data bus, a segmented global data bus coupled to the local data bus, and a section select switch that is configurable to direct a signal from the local data bus to either end of the segmented global data bus. Provided also is a computational device comprising a processor and the memory device and optionally a display. Provided also is a method in which a signal is received from a local data bus, and a section select switch is configured to direct the signal from the local data bus to either end of a segmented global data bus.
-
-
-
-
-
-
-
-
-
Search Results
30
records
(took 0.021 seconds)
