公开(公告)号：US20190008029A1

公开(公告)日：2019-01-03

申请号：US16021618

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Khang Choong Yong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Stephen Harvey Hall ,  Yun Rou Lim

IPC: H05K1/02 ,  H01L23/498 ,  H01L23/64

Abstract: Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the conductor can include a first part routed over a major surface of a first side of the reference plane structure and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of a second side of the reference plane structure and that approaches a second edge of the reference plane structure with a second trajectory in-line with the first trajectory, and a third portion connecting the first portion with the second portion and having a third trajectory departing from the first trajectory and the second trajectory, the third portion configured to span the void.

公开(公告)号：US20180342467A1

公开(公告)日：2018-11-29

申请号：US15974393

申请日：2018-05-08

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/00 ,  H01L23/528 ,  H01L49/02

Abstract: Disclosed herein are integrated circuit (IC) structures with a conductive element coupled to a first surface of a package substrate, where the conductive element has cavities for embedding components and the embedded components are electrically connected to the conductive element, as well as related apparatuses and methods. In some embodiments, embedded components have one terminal end, which may be positioned vertically, with the terminal end facing into the cavity, and coupled to the conductive element. In some embodiments, embedded components have two terminal ends, which may be positioned vertically with one terminal end coupled to the conductive element and the other terminal end coupled to the package substrate. In some embodiments, embedded components include passive devices, such as capacitors, resistors, and inductors. In some embodiments, a conductive element is a stiffener.

公开(公告)号：US20180145014A1

公开(公告)日：2018-05-24

申请号：US15666448

申请日：2017-08-01

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2924/207

Abstract: An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body.

公开(公告)号：US20170075388A1

公开(公告)日：2017-03-16

申请号：US14852592

申请日：2015-09-13

Applicant: Intel Corporation

Inventor： Chee Chun Yee ,  David W. Browning ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Min Suet Lim ,  Howe Yin Loo ,  Poh Tat Oh

IPC: G06F1/16 ,  G06F3/041

CPC classification number: G06F1/1652 ,  G06F1/1626 ,  G06F1/1641 ,  G06F1/1643 ,  G06F1/1675 ,  G06F3/041 ,  G06F2203/04102

Abstract: A computing device includes a flexible display screen, a housing to house at least one processor device and at least one memory element, and a first wing to support a side portion of the display screen. The front face of the housing includes a center portion of the display screen. The first wing is connected to the housing by a hinge, the first wing configured to swivel about an axis defined by the hinge. The hinge is configured to lock the first wing in at least two wing positions, a first of the wing positions supports the side portion of the display screen in a first orientation, a second of the wing positions supports the side portion of the display screen in a second orientation, and the side portion of the display screen is active in the first orientation and hidden in the second orientation.

Abstract translation: 计算设备包括柔性显示屏，用于容纳至少一个处理器设备的壳体和至少一个存储器元件，以及支撑显示屏幕的侧面部分的第一翼片。 壳体的前表面包括显示屏的中心部分。 第一翼通过铰链连接到壳体，第一翼构造成围绕由铰链限定的轴线旋转。 所述铰链被构造成将所述第一翼片锁定在至少两个翼位置中，所述机翼位置中的第一翼位置以第一方向支撑所述显示屏的侧部，所述翼位置中的第二翼支撑所述显示屏幕的侧部 第二取向，并且显示屏幕的侧部在第一取向中是有效的，并且在第二取向中被隐藏。

公开(公告)号：US09478524B2

公开(公告)日：2016-10-25

申请号：US14852013

申请日：2015-09-11

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi ,  Jackson Chung Peng Kong

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/06183 ,  H01L2224/06189 ,  H01L2224/06517 ,  H01L2224/131 ,  H01L2224/16137 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17183 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80894 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.

Abstract translation: 描述了具有中间垂直侧芯片的半导体多管芯结构以及容纳这种半导体多管芯结构的封装。 在一个示例中，多管芯半导体结构包括具有半导体管芯的第一基本水平布置的第一主堆叠管芯（MSD）结构。 还包括具有半导体管芯的第二基本水平布置的第二MSD结构。 中间垂直侧芯片（i-VSC）设置在电耦合到第一和第二MSD结构之间。

公开(公告)号：US20160211619A1

公开(公告)日：2016-07-21

申请号：US14601403

申请日：2015-01-21

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Howard L Heck ,  Kuan-Yu Chen ,  Boon Ping Koh ,  Min Keen Tang ,  Kooi Chi Ooi

IPC: H01R13/648 ,  H01R24/66

CPC classification number: H01R13/6485 ,  H01R24/66 ,  H01R2107/00

Abstract: In one example an electronic device comprises a housing. A receptacle in the housing comprising an opening at a distal end to receive a plug and an electrostatic conductor assembly positioned proximate the opening in the receptacle, wherein the electrostatic conductor assembly is coupled to a dedicated electrical discharge path. Other examples may be described.

Abstract translation: 在一个示例中，电子设备包括壳体。 壳体中的容器包括在远端处的开口，用于容纳插头和靠近插座中的开口定位的静电导体组件，其中静电导体组件耦合到专用放电路径。 可以描述其他示例。

公开(公告)号：US12183722B2

公开(公告)日：2024-12-31

申请号：US17638039

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11 ,  H01L49/02

Abstract: Disclosed embodiments include molded interconnect bridges that are in a molded frame, where the molded frame includes passive devices that couple to a metal buildup layer that includes at least one power rail and one ground rail. The molded interconnects bridge is embedded in an integrated-circuit package substrate between a die side and a land side, and closer to the die side.

公开(公告)号：US12033953B2

公开(公告)日：2024-07-09

申请号：US16830853

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Tin Poay Chuah ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/3025

Abstract: A substrate may be included in an electronic device. The substrate may include a first layer that may include a dielectric material. The first layer may define a substrate surface. The substrate may include a second layer optionally including the dielectric material. The second layer may be coupled to the first layer. A wiring trace may be located in the substrate. A recess may extend through the substrate surface, the first layer, and may extend through the second layer. A substrate interconnect may be located within the recess. The substrate interconnect may be at least partially located below the substrate surface. The substrate interconnect may be in electrical communication with the wiring trace.

公开(公告)号：US11955431B2

公开(公告)日：2024-04-09

申请号：US16987437

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Saravanan Sethuraman

IPC: H01L23/49 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5386 ,  H01L23/552

Abstract: Semiconductor packages, and methods for making the semiconductor packages, having an interposer structure with one or more interposer and an extension platform, which has an opening for placing the interposer, and the space between the interposer and the extension platform is filled with a polymeric material to form a unitary interposer-extension platform composite structure. A stacked structure may be formed by at least a first semiconductor chip coupled to the interposer and at least a second semiconductor chip coupled to the extension platform, and at least one bridge extending over the space that electrically couples the extension platform and the interposer. The extension platform may include a recess step section that may accommodate a plurality of passive devices to reduced power delivery inductance loop for the high-density 2.5D and 3D stacked packaging applications.

公开(公告)号：US11887940B2

公开(公告)日：2024-01-30

申请号：US17125593

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/50 ,  H01L23/13 ,  H01L23/498 ,  H01L49/02

CPC classification number: H01L23/562 ,  H01L23/13 ,  H01L23/50 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/32 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/19105

Abstract: Disclosed herein are integrated circuit (IC) structures with a conductive element coupled to a first surface of a package substrate, where the conductive element has cavities for embedding components and the embedded components are electrically connected to the conductive element, as well as related apparatuses and methods. In some embodiments, embedded components have one terminal end, which may be positioned vertically, with the terminal end facing into the cavity, and coupled to the conductive element. In some embodiments, embedded components have two terminal ends, which may be positioned vertically with one terminal end coupled to the conductive element and the other terminal end coupled to the package substrate. In some embodiments, embedded components include passive devices, such as capacitors, resistors, and inductors. In some embodiments, a conductive element is a stiffener.