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公开(公告)号:US11862552B2
公开(公告)日:2024-01-02
申请号:US17567639
申请日:2022-01-03
Applicant: INTEL CORPORATION
Inventor: Sai Vadlamani , Prithwish Chatterjee , Robert A. May , Rahul S. Jain , Lauren A. Link , Andrew J. Brown , Kyu Oh Lee , Sheng C. Li
CPC classification number: H01L23/49838 , H01F17/0013 , H01F17/0033 , H01F27/2804 , H01F27/40 , H01F41/043 , H01F41/046 , H01L21/486 , H01L21/4853 , H01L21/4857 , H01L23/498 , H01L23/49811 , H01L23/49822 , H01L23/49866 , H01L24/19 , H01L24/20 , H05K1/00 , H01F2017/0066 , H01F2027/2809 , H01L24/16 , H01L24/48 , H01L24/81 , H01L2224/16157 , H01L2224/16227 , H01L2224/48227 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81447 , H01L2224/81815 , H01L2924/00014 , H01L2924/19042 , H01L2924/19102 , H01L2224/81815 , H01L2924/00014 , H01L2224/81447 , H01L2924/00014 , H01L2924/00014 , H01L2224/45099
Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.
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22.
公开(公告)号:US11842981B2
公开(公告)日:2023-12-12
申请号:US17466842
申请日:2021-09-03
Applicant: Intel Corporation
Inventor: Rahul Jain , Ji Yong Park , Kyu Oh Lee
IPC: H01L23/00 , H01L25/00 , H01L23/538 , H01L25/065
CPC classification number: H01L24/81 , H01L23/5385 , H01L24/17 , H01L25/0652 , H01L25/50 , H01L23/5383 , H01L23/5384 , H01L2224/16113 , H01L2224/16235
Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
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公开(公告)号:US11664290B2
公开(公告)日:2023-05-30
申请号:US17459993
申请日:2021-08-27
Applicant: INTEL CORPORATION
Inventor: Rahul Jain , Kyu Oh Lee , Siddharth K. Alur , Wei-Lun K. Jen , Vipul V. Mehta , Ashish Dhall , Sri Chaitra J. Chavali , Rahul N. Manepalli , Amruthavalli P. Alur , Sai Vadlamani
IPC: H01L23/31 , H01L21/48 , H01L21/56 , H01L23/498 , H01L23/532 , H01L23/538 , H01L23/00 , H01L25/065
CPC classification number: H01L23/3185 , H01L21/4853 , H01L21/4857 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L23/5381 , H01L23/5383 , H01L23/5386 , H01L23/53295 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2224/16227 , H01L2224/81 , H01L2224/83051 , H01L2924/18161
Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20230162902A1
公开(公告)日:2023-05-25
申请号:US17531954
申请日:2021-11-22
Applicant: Intel Corporation
Inventor: Numair Ahmed , Kyu Oh Lee , Sri Chaitra Jyotsna Chavali , Vijaya Boddu , Krishna Bharath , Robert L. Sankman
IPC: H01F27/02 , H01F41/02 , H01L23/498 , H01L21/48
CPC classification number: H01F27/022 , H01F41/0206 , H01L23/49822 , H01L23/49827 , H01L21/4857 , H01L21/486
Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a package with integrated inductors. In selected examples, the package includes a core layer having a core thickness and through holes. The package further includes inductor structures within the through holes, such that an inductor structure has a length exceeding the core thickness.
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公开(公告)号:US11651885B2
公开(公告)日:2023-05-16
申请号:US16637006
申请日:2017-09-28
Applicant: Intel Corporation
Inventor: Junnan Zhao , Ying Wang , Cheng Xu , Kyu Oh Lee , Sheng Li , Yikang Deng
IPC: H01F17/00 , H01F27/255
CPC classification number: H01F17/0013 , H01F27/255 , H01F2017/002 , H01F2017/0066
Abstract: Described herein are magnetic core inductors (MCI) and methods for manufacturing magnetic core inductors. A first embodiment of the MCI can be a snake-configuration MCI. The snake-configuration MCI can be formed by creating an opening in a base material, such as copper, and providing a nonconductive magnetic material in the opening. The inductor can be further formed by forming plated through holes into the core material. The conductive elements for the inductor can be formed in the plated through holes. The nonconductive magnetic material surrounds each conductive element and plated through hole. In embodiments, a layered coil inductor can be formed by drilling a laminate to form a cavity through the laminate within the metal rings of the layered coil inductor. The nonconductive magnetic material can be provided in the cavity.
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26.
公开(公告)号:US11610706B2
公开(公告)日:2023-03-21
申请号:US15870302
申请日:2018-01-12
Applicant: Intel Corporation
Inventor: Sai Vadlamani , Prithwish Chatterjee , Rahul Jain , Kyu Oh Lee , Sheng C. Li , Andrew J. Brown , Lauren A. Link
IPC: H01F1/42 , H01F27/38 , B32B27/38 , C22C45/04 , H01F17/00 , H01L23/498 , H01F27/28 , H01L21/56 , H01F17/06
Abstract: A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.
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公开(公告)号:US11251113B2
公开(公告)日:2022-02-15
申请号:US15855453
申请日:2017-12-27
Applicant: Intel Corporation
Inventor: Sai Vadlamani , Prithwish Chatterjee , Robert A. May , Rahul S. Jain , Lauren A. Link , Andrew J. Brown , Kyu Oh Lee , Sheng C. Li
Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.
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公开(公告)号:US11217534B2
公开(公告)日:2022-01-04
申请号:US16646932
申请日:2017-12-30
Applicant: Intel Corporation
Inventor: Cheng Xu , Junnan Zhao , Ji Yong Park , Kyu Oh Lee
IPC: H01L23/538 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/00 , H01L25/065 , H01L23/498
Abstract: Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.
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公开(公告)号:US11031360B2
公开(公告)日:2021-06-08
申请号:US16990782
申请日:2020-08-11
Applicant: Intel Corporation
Inventor: Cheng Xu , Yikang Deng , Kyu Oh Lee , Ji Yong Park , Srinivas Pietambaram , Ying Wang , Chong Zhang , Rui Zhang , Junnan Zhao
IPC: H01L23/64 , H05K1/16 , H01L23/522 , H01L23/528 , H01F27/24 , H01L27/04 , H01F27/28 , H01L21/822
Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.
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公开(公告)号:US20200211927A1
公开(公告)日:2020-07-02
申请号:US16233808
申请日:2018-12-27
Applicant: Intel Corporation
Inventor: Zhimin Wan , Cheng Xu , Yikang Deng , Junnan Zhao , Ying Wang , Chong Zhang , Kyu Oh Lee , Chandra Mohan Jha , Chia-Pin Chiu
IPC: H01L23/473 , H01L21/48
Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.
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