Magnetic core inductors
    25.
    发明授权

    公开(公告)号:US11651885B2

    公开(公告)日:2023-05-16

    申请号:US16637006

    申请日:2017-09-28

    CPC classification number: H01F17/0013 H01F27/255 H01F2017/002 H01F2017/0066

    Abstract: Described herein are magnetic core inductors (MCI) and methods for manufacturing magnetic core inductors. A first embodiment of the MCI can be a snake-configuration MCI. The snake-configuration MCI can be formed by creating an opening in a base material, such as copper, and providing a nonconductive magnetic material in the opening. The inductor can be further formed by forming plated through holes into the core material. The conductive elements for the inductor can be formed in the plated through holes. The nonconductive magnetic material surrounds each conductive element and plated through hole. In embodiments, a layered coil inductor can be formed by drilling a laminate to form a cavity through the laminate within the metal rings of the layered coil inductor. The nonconductive magnetic material can be provided in the cavity.

    Galvanic corrosion protection for semiconductor packages

    公开(公告)号:US11217534B2

    公开(公告)日:2022-01-04

    申请号:US16646932

    申请日:2017-12-30

    Abstract: Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.

    MICROELECTRONIC ASSEMBLIES HAVING A COOLING CHANNEL

    公开(公告)号:US20200211927A1

    公开(公告)日:2020-07-02

    申请号:US16233808

    申请日:2018-12-27

    Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.

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