公开(公告)号：US20200286687A1

公开(公告)日：2020-09-10

申请号：US16296085

申请日：2019-03-07

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Nazila Haratipour ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H01L27/108 ,  H01L49/02 ,  G11C11/22

Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.

公开(公告)号：US20190386203A1

公开(公告)日：2019-12-19

申请号：US16012673

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-Ching Lin ,  Sasikanth Manipatruni ,  Ian Young

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01F10/32

Abstract: An apparatus is provided which comprises: a bit-line; a first word-line; a second word-line; and a source-line; a magnetic junction comprising a free magnet; an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the free magnet of the magnetic junction; and a first device (e.g., a selector device) coupled at one end of the interconnect and to the second word-line; and a second device coupled to the magnetic junction, the first word-line and the source-line.

公开(公告)号：US20250140649A1

公开(公告)日：2025-05-01

申请号：US18498340

申请日：2023-10-31

Applicant: Intel corporation

Inventor： Feng Zhang ,  Tao Chu ,  Minwoo Jang ,  Yanbin Luo ,  Guowei Xu ,  Ting-Hsiang Hung ,  Chiao-Ti Huang ,  Robin Chao ,  Chia-Ching Lin ,  Yang Zhang ,  Kan Zhang

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/778 ,  H01L29/786

Abstract: An IC device may include a semiconductor structure and a backside semiconductor structure over the semiconductor structure. The semiconductor structure and backside semiconductor structure may constitute the source or drain region of a transistor. The backside semiconductor structure may be closer to the backside of a substrate of the IC device than the semiconductor structure. The backside semiconductor structure may be formed at a lower temperature than the semiconductor structure. The backside semiconductor structure may have one or more different materials from the semiconductor structure. For instance, a semiconductor material in the backside semiconductor structure may have a different crystal direction from a semiconductor material in the semiconductor structure. As another example, the backside semiconductor structure may have one or more different chemical compounds from the semiconductor structure. The backside semiconductor structure may be over a backside via that can couple the backside semiconductor structure to a backside metal layer.

公开(公告)号：US20250112122A1

公开(公告)日：2025-04-03

申请号：US18477906

申请日：2023-09-29

Applicant: INTEL CORPORATION

Inventor： Kevin P. O'Brien ,  Paul Gutwin ,  David L. Kencke ,  Mahmut Sami Kavrik ,  Daniel Chanemougame ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Kirby Maxey ,  Uygar E. Avci ,  Tristan A. Tronic ,  Chelsey Dorow ,  Andrey Vyatskikh ,  Rachel A. Steinhardt ,  Chia-Ching Lin ,  Chi-Yin Cheng ,  Yu-Jin Chen ,  Tyrone Wilson

IPC: H01L23/48 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/18 ,  H01L29/423 ,  H01L29/78

Abstract: Integrated circuit (IC) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.

公开(公告)号：US20250107147A1

公开(公告)日：2025-03-27

申请号：US18476248

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Uygar E. Avci ,  Pratyush P. Buragohain ,  Chelsey Dorow ,  Jack T. Kavalieros ,  Chia-Ching Lin ,  Matthew V. Metz ,  Wouter Mortelmans ,  Carl Hugo Naylor ,  Kevin P. O'Brien ,  Ashish Verma Penumatcha ,  Carly Rogan ,  Rachel A. Steinhardt ,  Tristan A. Tronic ,  Andrey Vyatskikh

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/46 ,  H01L27/092 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76

Abstract: Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.

公开(公告)号：US20250006434A1

公开(公告)日：2025-01-02

申请号：US18883126

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Owen Y. Loh ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H10B12/00

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.

公开(公告)号：US20240222484A1

公开(公告)日：2024-07-04

申请号：US18092152

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Kevin P. O'Brien ,  Ashish Verma Penumatcha ,  Chelsey Dorow ,  Kirby Maxey ,  Carl H. Naylor ,  Tao Chu ,  Guowei Xu ,  Uygar Avci ,  Feng Zhang ,  Ting-Hsiang Hung ,  Ande Kitamura ,  Mahmut Sami Kavrik

IPC: H01L29/76 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7606 ,  H01L21/02568 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/775

Abstract: Transistors and integrated circuitry including a 2D channel material layer within a stack of material layers further including one or more insulator (e.g., dielectric) materials above and/or below the 2D channel material layer. These supporting insulator layers may be non-sacrificial while other material layers within a starting material stack may be sacrificial, replaced, for example, with gate insulator and/or gate material. In some exemplary embodiments, the 2D channel material is a metal chalcogenide and the supporting insulator layer is advantageously a dielectric material composition having a low dielectric constant.

公开(公告)号：US20240222441A1

公开(公告)日：2024-07-04

申请号：US18091197

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Carl Naylor ,  Chelsey Dorow ,  Chia-Ching Lin ,  Dominique Adams ,  Kevin O'Brien ,  Matthew Metz ,  Scott Clendenning ,  Sudarat Lee ,  Tristan Tronic ,  Uygar Avci

IPC: H01L29/40 ,  H01L21/04 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/44 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/401 ,  H01L21/043 ,  H01L21/044 ,  H01L21/28264 ,  H01L21/32136 ,  H01L21/44 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/454 ,  H01L29/78648 ,  H01L29/4908

Abstract: Devices, transistor structures, systems, and techniques, are described herein related to selective gate oxide formation on 2D materials for transistor devices. A transistor structure includes a gate dielectric structure on a 2D semiconductor material layer, and source and drain structures in contact with the gate dielectric structure and on the 2D semiconductor material layer. The source and drain structures include a metal material or metal nitride material and the gate dielectric structure includes an oxide of the metal material or metal nitride material.

公开(公告)号：US20240206348A1

公开(公告)日：2024-06-20

申请号：US18083493

申请日：2022-12-17

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Hai Li

IPC: H10N52/85 ,  G11C11/16 ,  H03K19/20 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85

CPC classification number: H10N52/85 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H03K19/20 ,  H10B61/22 ,  H10N50/10 ,  H10N50/85

Abstract: In embodiments herein, probabilistic and deterministic logic devices include reduced symmetry materials, such as two-dimensional (2D) transition metal dichalcogenide (TMD) materials (e.g., NbSe2 or MoTe2).

公开(公告)号：US20240088217A1

公开(公告)日：2024-03-14

申请号：US17940195

申请日：2022-09-08

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Chia-Ching Lin ,  Yanbin Luo ,  Ting-Hsiang Hung ,  Feng Zhang ,  Guowei Xu

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L29/7856

Abstract: Techniques are provided herein to form semiconductor devices that include a layer across an upper surface of a dielectric fill between devices and configured to prevent or otherwise reduce recessing of the dielectric fill. In this manner, the layer may be referred to as a barrier layer or recess-inhibiting layer. The semiconductor regions of the devices extend above a subfin region that may be native to the substrate. These subfin regions are separated from one another using a dielectric fill that acts as a shallow trench isolation (STI) structure to electrically isolate devices from one another. A barrier layer is formed over the dielectric fill early in the fabrication process to prevent or otherwise reduce the dielectric fill from recessing during subsequent processing. The layer may include oxygen and a metal, such as aluminum.