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    Run to run control process for controlling critical dimensions
    22.
    再颁专利
    Run to run control process for controlling critical dimensions 有权
    运行以运行控制过程以控制关键尺寸

    公开(公告)号：USRE39518E1

    公开(公告)日：2007-03-13

    申请号：US09908390

    申请日：2001-07-18

    申请人： Anthony John Toprac ,  Douglas John Downey ,  Subhash Gupta

    发明人： Anthony John Toprac ,  Douglas John Downey ,  Subhash Gupta

    IPC分类号： H01L21/66 ,  H01L21/302

    CPC分类号： H01L22/20

    摘要： It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated variable in either a feedforward or a feedback control configuration to control critical dimension variation during semiconductor fabrication. By controlling critical dimensions through the adjustment of photoresist etch time, many advantages are achieved including a reduced lot-to-lot variation, an increased yield, and increased speed of the fabricated circuits. In one embodiment these advantages are achieved for polysilicon gate critical dimension control in microprocessor circuits. Polysilicon gate linewidth variability is reduced using a control method using either feedforward and feedback or feedback alone. In some embodiments, feedback control is implemented for controlling critical dimensions using photoresist each time as a manipulated variable. In an alternative embodiment, critical dimensions are controlled using RF power as a manipulated variable. A run-to-run control technique is used to drive the critical dimensions of integrated circuits to a set specification. In a run-to-run control technique a wafer test or measurement is made and a process control recipe is adjusted based on the result of the test or measurement on a run-by-run basis. The run-to-run control technique is applied to drive the critical dimensions of a polysilicon gate structure to a target specification. The run-to-run control technique is applied to drive the critical dimensions in an integrated circuit to a defined specification using photoresist etch time as a manipulated variable.

    摘要翻译： 已经发现，已知和未知的关键尺寸变化的所有原因通过调整光致抗蚀剂蚀刻的时间来补偿。 因此，控制方法采用使用光致抗蚀剂蚀刻时间的控制系统作为前馈或反馈控制配置中的操纵变量来控制半导体制造期间的临界尺寸变化。 通过调整光致抗蚀剂蚀刻时间来控制关键尺寸，实现了许多优点，包括减少的批次批量变化，增加的产量和增加的制造电路的速度。 在一个实施例中，对微处理器电路中的多晶硅栅极关键尺寸控制实现了这些优点。 使用仅使用前馈和反馈或反馈的控制方法来减少多晶硅栅极线宽变化。 在一些实施例中，实施反馈控制以用于每次作为操纵变量来控制使用光致抗蚀剂的临界尺寸。 在替代实施例中，使用RF功率作为操纵变量来控制临界尺寸。 运行运行控制技术用于将集成电路的关键尺寸驱动到设定规格。 在运行到运行的控制技术中，进行晶片测试或测量，并且基于逐个运行的测试或测量的结果来调整过程控制配方。 运行运行控制技术用于将多晶硅栅极结构的关键尺寸驱动到目标规格。 应用运行控制技术将集成电路中的关键尺寸驱动到使用光刻胶蚀刻时间作为操作变量的规定规格。

    Method for bonding wafers to produce stacked integrated circuits
    23.
    发明申请
    Method for bonding wafers to produce stacked integrated circuits 审中-公开
    用于接合晶片以产生堆叠集成电路的方法

    公开(公告)号：US20050224921A1

    公开(公告)日：2005-10-13

    申请号：US11150879

    申请日：2005-06-09

    申请人： Subhash Gupta ,  Paul Ho ,  Sangki Hong

    发明人： Subhash Gupta ,  Paul Ho ,  Sangki Hong

    IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L29/40 ,  H01L21/461

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08148 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

    摘要： An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. An integrated circuit wafer according to the present invention includes a substrate having first and second surfaces constructed from a wafer material, the first surface having a circuit layer that includes integrated circuit elements constructed thereon. A plurality of vias extend from the first surface through the circuit layer and terminate in the substrate at a first distance from the first surface. The vias include a stop layer located in the bottom of each via constructed from a stop material that is more resistant to chemical/mechanical polishing (CMP) than the wafer material. The vias may be filled with an electrically conducting material to provide vertical connections between the various circuit layers in a stacked integrated circuit. In this case, the electrical conducting vias are also connected to various circuit elements by metallic conductors disposed in a dielectric layer that covers the circuit layer. A plurality of bonding pads are provided on one surface of the integrated circuit wafer. These pads may be part of the vias. These pads preferably extend above the surface of the integrated circuit wafer. A stacked integrated circuit according to the present invention is constructed by bonding two integrated circuit wafers together utilizing the bonding pads. One of the integrated circuit wafers is then thinned to a predetermined thickness determined by the depth of the vias by chemical/mechanical polishing (CMP) of the surface of that integrated circuit wafer that is not bonded to the other integrated circuit wafer, the stop layer in the vias preventing the CMP from removing wafer material that is within the first distance from the first surface of the substrate of the wafer being thinned.

    摘要翻译： 一种集成电路晶片元件和用于将其结合以产生堆叠集成电路的改进方法。 根据本发明的集成电路晶片包括具有由晶片材料构成的第一和第二表面的基板，所述第一表面具有包括在其上构成的集成电路元件的电路层。 多个通孔从第一表面延伸穿过电路层，并在离开第一表面的第一距离处终止在基板中。 通孔包括位于每个通孔底部的停止层，该停止层由比晶片材料更耐化学/机械抛光（CMP）的止动材料构成。 通孔可以填充有导电材料，以在堆叠集成电路中的各个电路层之间提供垂直连接。 在这种情况下，导电通孔也通过布置在覆盖电路层的电介质层中的金属导体连接到各种电路元件。 多个接合焊盘设置在集成电路晶片的一个表面上。 这些焊盘可以是通孔的一部分。 这些焊盘优选地在集成电路晶片的表面上方延伸。 根据本发明的堆叠集成电路是通过使用接合焊盘将两个集成电路晶片结合在一起而构成的。 然后通过化学/机械抛光（CMP）将集成电路晶片之一变薄到由通孔的深度确定的预定厚度，该集成电路晶片的表面未结合到另一集成电路晶片，停止层 在通孔中，防止CMP从晶片的衬底的第一表面的第一距离内移除晶片材料。

    Method for stripping copper in damascene interconnects
    26.
    发明授权
    Method for stripping copper in damascene interconnects 有权

    公开(公告)号：US06565664B2

    公开(公告)日：2003-05-20

    申请号：US10131519

    申请日：2002-04-24

    申请人： Subhash Gupta ,  Simon Chooi ,  Paul Ho ,  Mei Sheng Zhou

    发明人： Subhash Gupta ,  Simon Chooi ,  Paul Ho ,  Mei Sheng Zhou

    IPC分类号： C23G114

    CPC分类号： H01L21/32134 ,  C23F1/34 ,  H01L21/7684 ,  Y10S134/902

    摘要： An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.

    Dual layer pattern formation method for dual damascene interconnect
    27.
    发明授权
    Dual layer pattern formation method for dual damascene interconnect 有权
    双镶嵌互连的双层图案形成方法

    公开(公告)号：US06465157B1

    公开(公告)日：2002-10-15

    申请号：US09494638

    申请日：2000-01-31

    申请人： Jianxun Li ,  Mei Sheng Zhou ,  Subhash Gupta ,  Ming hui Far

    发明人： Jianxun Li ,  Mei Sheng Zhou ,  Subhash Gupta ,  Ming hui Far

    IPC分类号： G03F700

    CPC分类号： H01L21/76811

    摘要： A new method of forming dual damascene interconnects has been achieved. A semiconductor substrate is provided. A dielectric layer is provided overlying the semiconductor substrate. A first photoresist layer is deposited overlying the dielectric layer. The first photoresist layer is exposed, but not developed, to define patterns where via trenches are planned. A second photoresist layer is deposited overlying the first photoresist layer. The second photoresist layer is exposed to define patterns where interconnect trenches are planned. The second photoresist layer and the first photoresist layer are developed to complete the via trench pattern of the first photoresist layer and the interconnect trench pattern of the second photoresist layer. The dielectric layer is etched through where defined by the via trench pattern of the first photoresist layer. The dielectric layer is etch where defined by the interconnect pattern of the second photoresist layer, and the dual damascene interconnect of the integrated circuit device is completed.

    摘要翻译： 已经实现了形成双镶嵌互连的新方法。 提供半导体衬底。 提供覆盖在半导体衬底上的电介质层。 沉积在介电层上的第一光致抗蚀剂层。 第一光致抗蚀剂层被暴露但未显影，以限定通过沟槽被规划的图案。 第二光致抗蚀剂层沉积在第一光致抗蚀剂层上。 暴露第二光致抗蚀剂层以限定互连沟槽被计划的图案。 显影第二光致抗蚀剂层和第一光致抗蚀剂层以完成第一光致抗蚀剂层的通孔沟槽图案和第二光致抗蚀剂层的互连沟槽图案。 电介质层被蚀刻到由第一光致抗蚀剂层的通孔沟槽图案限定的位置。 介电层是由第二光致抗蚀剂层的互连图案限定的蚀刻，并且完成集成电路器件的双镶嵌互连。

    Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects
    30.
    发明授权
    Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects 失效
    将富硅材料集成在双镶嵌互连的自对准通孔中

    公开(公告)号：US06350675B1

    公开(公告)日：2002-02-26

    申请号：US09686282

    申请日：2000-10-12

    申请人： Simon Chooi ,  Mei-Sheng Zhou ,  Subhash Gupta ,  Yi Xu

    发明人： Simon Chooi ,  Mei-Sheng Zhou ,  Subhash Gupta ,  Yi Xu

    IPC分类号： H01L214763

    CPC分类号： H01L21/76832 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826

    摘要： This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates low dielectric constant intermetal dielectrics (IMD) and utilizes silylated top surface imaging (TSI) photoresist, with a single or multi-step selective reactive ion etch (RIE) process, to form trench/via opening. The invention incorporates the use of a silylated top surface imaging (TSI) resist etch barrier layer to form the via pattern, in the first level of a dual damascene process. Two variations of using the top surface imaging (TSI) resist, with and without leaving an exposed region in place, are described in the first and second embodiment of the invention, and in addition, a thin dielectric layer is made use of just below the resist layer. Provided adhesion between the top surface imaging (TSI) photoresist and the low dielectric constant intermetal dielectric (IMD) is good, the thin dielectric layer described above can be omitted, yielding the third and fourth embodiment of the invention. Special attention in the process is given to protecting the integrity of the low dielectric constant intermetal dielectric (ILD) material, selected from the group consisting of organic based or carbon doped silicon dioxide.

    摘要翻译： 本发明涉及用于半导体集成电路器件的制造方法，更具体地说，涉及形成自对准的双镶嵌互连和通孔，其结合了低介电常数金属间电介质（IMD）并利用甲硅烷基化的顶表面成像（TSI ）光致抗蚀剂，具有单步或多步选择性反应离子蚀刻（RIE）工艺，以形成沟槽/通孔。 本发明包括在双镶嵌工艺的第一水平中使用甲硅烷基化的顶表面成像（TSI）抗蚀剂蚀刻阻挡层以形成通孔图案。 在本发明的第一和第二实施例中描述了使用顶表面成像（TSI）抗蚀剂的两种变型，其具有和不具有将暴露区域保持在适当位置，此外，使用刚好低于 抗蚀剂层。 提供顶表面成像（TSI）光致抗蚀剂和低介电常数金属间电介质（IMD）之间的粘附性是好的，可以省略上述薄介电层，产生本发明的第三和第四实施例。 该方法中特别注意保护低介电常数金属间电介质（ILD）材料的完整性，该材料选自有机基或掺碳二氧化硅。