公开(公告)号：US08660641B2

公开(公告)日：2014-02-25

申请号：US12807861

申请日：2010-09-15

Applicant: Shinji Kakei ,  Jongho Lee ,  Yasuhiro Kagamihara

Inventor： Shinji Kakei ,  Jongho Lee ,  Yasuhiro Kagamihara

IPC: A61B5/0488

CPC classification number: A61B5/4528 ,  A61B5/0488 ,  A61B5/11 ,  A61B5/1121 ,  A61B5/4064 ,  A61B5/6824

Abstract: The present invention provides a system for evaluating motor control function in the brain. This system is for evaluating the motor control function in the brain of a subject from the electromyogram (EMG) data of joint prime movers and the data on the position, velocity and acceleration of the joint, wherein both of the data have been obtained by measuring a target-tracking movement performed by the subject with a motion measurement unit that tracks a moving target, the system comprising the following means (a) to (c): (a) means for separating the frequencies of the EMG data and the frequencies of the data on the position, velocity and acceleration into a plurality of frequency components; (b) means for determining the ratio of viscosity coefficient to elastic coefficient (B/K ratio) for each of the frequency components by applying the EMG data and the data on the position, velocity and acceleration to a specific movement equation; and (c) means for evaluating the causal relationship between the motor control function in the brain and the target-tacking movement using the B/K ratio as an index.

Abstract translation: 本发明提供一种用于评估大脑中的运动控制功能的系统。 该系统用于从关节原动机的肌电图（EMG）数据和关节的位置，速度和加速度数据中评估受试者的脑中的运动控制功能，其中两个数据都是通过测量获得的 由跟踪移动目标的运动测量单元由对象执行的目标跟踪运动，该系统包括以下装置（a）至（c）：（a）用于将EMG数据的频率和频率分离的装置 关于位置，速度和加速度进入多个频率分量的数据; （b）通过将EMG数据和关于位置，速度和加速度的数据应用于特定运动方程来确定每个频率分量的粘度系数与弹性系数（B / K比）的比率的装置; 和（c）使用B / K比作为指标来评估大脑中的运动控制功能与目标定位运动之间的因果关系的装置。

公开(公告)号：US20130020720A1

公开(公告)日：2013-01-24

申请号：US13546163

申请日：2012-07-11

Applicant: Young Lyong Kim ,  Taehoon Kim ,  Jongho Lee ,  Chul-Yong Jang

Inventor： Young Lyong Kim ,  Taehoon Kim ,  Jongho Lee ,  Chul-Yong Jang

IPC: H01L25/07

CPC classification number: H01L21/76802 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3185 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/24146 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2225/06524 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

公开(公告)号：US08029713B2

公开(公告)日：2011-10-04

申请号：US12244575

申请日：2008-10-02

Applicant: Jongho Lee

Inventor： Jongho Lee

IPC: B28B7/22

CPC classification number: B29C45/1635 ,  B29C45/27 ,  B29L2031/3005 ,  B60R13/0243

Abstract: A first mold has a core passage, and first and second cavities in fluid communication with each other at the core passage. A second mold has first and second nozzles therein that inject first and second resins to the first and second cavities, respectively. The core member is slidable within the core passage to provide or block the fluid communication between the cavities, and has a third nozzle therein to inject a third resin to the core passage. The first and second resins are injected into the cavities. The core member is moved to block the fluid communication between the cavities, before injecting the first and second resins is completed. The third resin is injected while moving the core member to provide the fluid communication, after injecting the first and second resins is completed. The molds are separated, thereby yielding a single molded product, such as a vehicle door trim.

Abstract translation: 第一模具具有芯通道，并且在芯通道处彼此流体连通的第一和第二空腔。 第二模具在其中具有分别将第一和第二树脂注入到第一和第二空腔中的第一和第二喷嘴。 芯构件可在芯通道内滑动以提供或阻挡空腔之间的流体连通，并且其中具有第三喷嘴以将第三树脂注入到芯通道。 将第一和第二树脂注入到空腔中。 在完成注入第一和第二树脂之前，移动芯构件以阻止空腔之间的流体连通。 在移动芯部件以提供流体连通时注入第三树脂，在完成注入第一和第二树脂之后。 模具被分离，从而产生单个模制产品，例如车门装饰件。

公开(公告)号：US20100096754A1

公开(公告)日：2010-04-22

申请号：US12588477

申请日：2009-10-16

Applicant: Jonggi Lee ,  SunWon Kang ,  Young Lyong Kim ,  Jongho Lee ,  Chul-Yong Jang ,  Minill Kim ,  Eunchul Ahn ,  Kwang Yong Lee ,  Seungduk Baek ,  Ji-Seok Hong

Inventor： Jonggi Lee ,  SunWon Kang ,  Young Lyong Kim ,  Jongho Lee ,  Chul-Yong Jang ,  Minill Kim ,  Eunchul Ahn ,  Kwang Yong Lee ,  Seungduk Baek ,  Ji-Seok Hong

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/13 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/06 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/1191 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Provided is a semiconductor package, a semiconductor module and a method for fabricating the semiconductor package. The method provides a substrate including a bonding pad. The method forms a dielectric layer for exposing the bonding pad on the substrate. The method forms a redistribution line which is electrically connected to the bonding pad, on the dielectric layer. The method forms an external terminal which is electrically connected to the bonding pad without using a solder mask which limits a position of the external terminal, on the redistribution line.

Abstract translation: 提供半导体封装，半导体模块和制造半导体封装的方法。 该方法提供了包括接合焊盘的衬底。 该方法形成用于使衬底上的焊盘露出的介电层。 该方法形成在电介质层上电连接到接合焊盘的再分配线。 该方法形成外部端子，该外部端子电连接到接合焊盘，而不使用在再分配线上限制外部端子的位置的焊接掩模。

公开(公告)号：US20100072593A1

公开(公告)日：2010-03-25

申请号：US12586565

申请日：2009-09-24

Applicant: Young Lyong Kim ,  Jongho Lee ,  Cheul-Joong Youn ,  Eunchul Ahn

Inventor： Young Lyong Kim ,  Jongho Lee ,  Cheul-Joong Youn ,  Eunchul Ahn

IPC: H01L23/495

CPC classification number: H01L23/49827 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49531 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a first package including at least one first semiconductor chip; a second package including an external connection terminal and at least one second semiconductor chip, the second package being stacked on the first package; and an interposer disposed between the first and second packages and connected to the external connection terminal to electrically connect the first and second packages to each other. The interposer comprises an intermediate connector having an exposed end portion to which the second package is electrically connected via the external connection terminal and a protruding end portion lower than the exposed end portion to which the first package is electrically connected.

Abstract translation: 半导体封装包括包括至少一个第一半导体芯片的第一封装; 包括外部连接端子和至少一个第二半导体芯片的第二封装，所述第二封装堆叠在所述第一封装上; 以及设置在第一和第二封装之间并且连接到外部连接端子以将第一和第二封装彼此电连接的插入器。 插入器包括具有暴露端部的中间连接器，第二封装经由外部连接端子电连接到该外部端部，以及比第一封装电连接到的暴露端部低的突出端部。

公开(公告)号：US07112539B2

公开(公告)日：2006-09-26

申请号：US10999608

申请日：2004-11-29

Applicant: Jongho Lee ,  Nae-In Lee

Inventor： Jongho Lee ,  Nae-In Lee

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises one or more ordered pairs of first and second layers. With the present invention, the dielectric constant of the high-k dielectric layer can be optimized while improving interface characteristics. With a higher crystallization temperature realized by forming the multi-layer structure, each of whose layers is not more than the critical thickness, leakage current can be reduced, thereby improving device performance.