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45 条记录 (耗时 0.027 秒)

    MIM capacitor in a copper damascene interconnect
    21.
    发明授权
    MIM capacitor in a copper damascene interconnect 有权
    MIM电容器在铜镶嵌互连中

    公开(公告)号：US07483258B2

    公开(公告)日：2009-01-27

    申请号：US11300567

    申请日：2005-12-13

    申请人： Chun-Hong Chen ,  Minghsing Tsai

    发明人： Chun-Hong Chen ,  Minghsing Tsai

    IPC分类号： H01G4/38

    CPC分类号： H01L23/5223 ,  H01L23/53228 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal-insulator-metal capacitor formed in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper capacitor plate includes the same pattern as the capacitor dielectric, the pattern having an area less than the area of the lower capacitor plate. The upper capacitor plate is formed of a second metal layer. The first and second metal layers may each be formed of cobalt, tungsten, nickel, molybdenum, or a combinations of one of the aforementioned elements with boron and/or phosphorus. Conductive vias provide contact from the upper capacitor plate and lower capacitor plate, to interconnect levels.

    摘要翻译： 形成在多电平半导体器件中的金属 - 绝缘体 - 金属电容器利用半导体器件的铜互连电平作为电容器的部分。 下电容器板由铜互连层和通过选择性沉积方法形成在铜互连层上的第一金属层组成。 上部电容器板包括与电容器电介质相同的图案，该图案具有小于下部电容器板的面积的面积。 上部电容器板由第二金属层形成。 第一和第二金属层可以各自由钴，钨，镍，钼或上述元素之一与硼和/或磷的组合形成。 导电通孔提供从上电容器板和下电容器板到互连电平的接触。

    Metal structure with sidewall passivation and method
    22.
    发明申请
    Metal structure with sidewall passivation and method 有权
    金属结构与侧壁钝化和方法

    公开(公告)号：US20060189143A1

    公开(公告)日：2006-08-24

    申请号：US11061350

    申请日：2005-02-18

    申请人： Minghsing Tsai ,  Yung-Cheng Lu

    发明人： Minghsing Tsai ,  Yung-Cheng Lu

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76834 ,  H01L21/02118 ,  H01L21/0226 ,  H01L21/3127 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76835

    摘要： A passivated metal structure and a method of forming the metal structure is disclosed. According to one embodiment, the patterned metal structure, such as conductive lines, are formed on a substrate. The copper lines are passivated by a polymer liner between the copper lines and a low k dielectric filling the spaces between the conductive lines. The polymer liner is preferably deposited on the sidewalls of the conductive lines by electro-grafting. The polymer liner may also be used in a damascene process according to a second embodiment.

    摘要翻译： 公开了钝化金属结构和形成金属结构的方法。 根据一个实施例，图案化的金属结构，例如导电线，形成在基板上。 铜线由铜线之间的聚合物衬垫和填充导电线之间的空间的低k电介质钝化。 聚合物衬垫优选通过电接枝沉积在导电线的侧壁上。 聚合物衬垫也可以用于根据第二实施例的镶嵌工艺中。

    Method for forming MIM capacitor in a copper damascene interconnect
    23.
    发明授权
    Method for forming MIM capacitor in a copper damascene interconnect 有权
    在铜镶嵌互连中形成MIM电容器的方法

    公开(公告)号：US08563391B2

    公开(公告)日：2013-10-22

    申请号：US12316956

    申请日：2008-12-17

    申请人： Chun-Hong Chen ,  Minghsing Tsai

    发明人： Chun-Hong Chen ,  Minghsing Tsai

    IPC分类号： H01L21/20

    CPC分类号： H01L23/5223 ,  H01L23/53228 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a metal-insulator-metal capacitor in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper capacitor plate includes the same pattern as the capacitor dielectric, the pattern having an area less than the area of the lower capacitor plate. The upper capacitor plate is formed of a second metal layer. The first and second metal layers may each be formed of cobalt, tungsten, nickel, molybdenum, or a combinations of one of the aforementioned elements with boron and/or phosphorus. Conductive vias provide contact from the upper capacitor plate and lower capacitor plate, to interconnect levels.

    摘要翻译： 在多电平半导体器件中形成金属 - 绝缘体 - 金属电容器的方法利用半导体器件的铜互连电平作为电容器的一部分。 下电容器板由铜互连层和通过选择性沉积方法形成在铜互连层上的第一金属层组成。 上部电容器板包括与电容器电介质相同的图案，该图案具有小于下部电容器板的面积的面积。 上部电容器板由第二金属层形成。 第一和第二金属层可以各自由钴，钨，镍，钼或上述元素之一与硼和/或磷的组合形成。 导电通孔提供从上电容器板和下电容器板到互连电平的接触。

    Approach for reducing copper line resistivity
    24.
    发明授权
    Approach for reducing copper line resistivity 有权
    降低铜线电阻率的方法

    公开(公告)号：US08242016B2

    公开(公告)日：2012-08-14

    申请号：US11803282

    申请日：2007-05-14

    申请人： Hsien-Ming Lee ,  Minghsing Tsai ,  Syun-Ming Jang

    发明人： Hsien-Ming Lee ,  Minghsing Tsai ,  Syun-Ming Jang

    IPC分类号： H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/76856 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873

    摘要： A method for fabricating an integrated circuit structure and the resulting integrated circuit structure are provided. The method includes forming a low-k dielectric layer; form an opening in the low-k dielectric layer; forming a barrier layer covering a bottom and sidewalls of the low-k dielectric layer; performing a treatment to the barrier layer in an environment comprising a treatment gas; and filling the opening with a conductive material, wherein the conductive material is on the barrier layer.

    摘要翻译： 提供一种用于制造集成电路结构的方法和所得到的集成电路结构。 该方法包括形成低k电介质层; 在低k电介质层中形成开口; 形成覆盖所述低k电介质层的底部和侧壁的阻挡层; 在包括处理气体的环境中对阻挡层进行处理; 并用导电材料填充开口，其中导电材料在阻挡层上。

    PROCESS APPARATUSES
    25.
    发明申请
    PROCESS APPARATUSES 有权
    过程设备

    公开(公告)号：US20070267461A1

    公开(公告)日：2007-11-22

    申请号：US11419933

    申请日：2006-05-23

    申请人： Chen-Hua Yu ,  Minghsing Tsai ,  Yi-Li Hsiao

    发明人： Chen-Hua Yu ,  Minghsing Tsai ,  Yi-Li Hsiao

    IPC分类号： A47J36/02

    CPC分类号： H01L21/67196 ,  H01L21/67017 ,  H01L21/76849 ,  H01L21/76883

    摘要： An apparatus includes an enclosure, at least one process chamber, a robot and at least one valve. The enclosure has a gas therein and at least one door configured to cover an opening into the enclosure. The gas includes at least one reduction gas. The robot is disposed within the enclosure and configured to transfer a substrate between the door and the process chamber. The valve is coupled to the enclosure.

    摘要翻译： 一种装置包括外壳，至少一个处理室，机​​器人和至少一个阀。 外壳中具有气体，并且至少一个门构造成覆盖到外壳中的开口。 气体包括至少一种还原气体。 机器人设置在外壳内并且构造成在门和处理室之间传送基板。 阀连接到外壳。

    Differentially metal doped copper damascenes
    26.
    发明申请
    Differentially metal doped copper damascenes 审中-公开
    差异化金属掺杂铜大马士革

    公开(公告)号：US20060091551A1

    公开(公告)日：2006-05-04

    申请号：US10977596

    申请日：2004-10-29

    申请人： Chun-Chieh Lin ,  Shih-Wei Chou ,  Minghsing Tsai

    发明人： Chun-Chieh Lin ,  Shih-Wei Chou ,  Minghsing Tsai

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L21/76816 ,  C25D3/58 ,  C25D5/022 ,  C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76877

    摘要： A method of forming a copper filled semiconductor feature having improved bulk properties including providing a semiconductor process wafer having a process surface including an opening for forming a semiconductor feature; depositing at least one metal dopant containing layer over the opening to form a thermally diffusive relationship to a subsequently deposited copper layer; depositing said copper layer to substantially fill the opening; and, thermally treating the semiconductor process wafer for a time period sufficient to distribute at least a portion of the metal dopants to collect along at least a portion of the periphery of said copper layer including a portion of said copper layer grain boundaries.

    摘要翻译： 一种形成具有改善的体积特性的铜填充半导体特征的方法，包括提供具有包括用于形成半导体特征的开口的工艺表面的半导体工艺晶片; 在所述开口上沉积至少一种含金属掺杂剂层以形成与随后沉积的铜层的热扩散关系; 沉积所述铜层以基本上填充所述开口; 以及对所述半导体工艺晶片进行热处理足以使所述金属掺杂剂的至少一部分分布在包含所述铜层晶界的一部分的所述铜层的周边的至少一部分的时间段内收集。

    Selective formation of metal gate for dual gate oxide application
    27.
    发明授权
    Selective formation of metal gate for dual gate oxide application 有权
    用于双栅极氧化物应用的金属栅极的选择性形成

    公开(公告)号：US06872627B2

    公开(公告)日：2005-03-29

    申请号：US09905408

    申请日：2001-07-16

    申请人： Sheng Hsiung Chen ,  Minghsing Tsai

    发明人： Sheng Hsiung Chen ,  Minghsing Tsai

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

    CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/908

    摘要： A new processing sequence is provided for the creation of a metal gate electrode. At least two polysilicon gate electrodes are provided over the surface of a substrate, these polysilicon gate electrodes having a relatively thick layer of gate dielectric making these polysilicon gate electrodes suitable for high-voltage applications. The two polysilicon gate electrodes are divided into a first and a second gate electrode, both gate electrodes are imbedded in a layer of Intra Metal Dielectric (IMD). The first gate electrode is removed by applying a lift-off process to this first gate electrode, creating an opening in the layer of IMD. The second gate structure is shielded by a photoresist mask during the removal of the first gate electrode. A metal gate electrode is created in the opening created in the layer of IMD, using a thin layer of gate dielectric.

    摘要翻译： 提供了新的处理顺序来创建金属栅电极。 在衬底的表面上设置至少两个多晶硅栅电极，这些多晶硅栅电极具有较厚的栅极电介质层，使得这些多晶硅栅电极适合于高电压应用。 两个多晶硅栅电极被分成第一和第二栅极，两个栅电极嵌入在金属介电层（IMD）中。 通过对该第一栅电极施加剥离工艺来除去第一栅电极，从而在IMD层中产生开口。 在去除第一栅极电极期间，第二栅极结构被光致抗蚀剂掩模屏蔽。 在IMD层中产生的开口中，使用薄的栅极电介质形成金属栅电极。

    Process for Improving Copper Line Cap Formation
    30.
    发明申请
    Process for Improving Copper Line Cap Formation 有权
    改善铜线帽形成的工艺

    公开(公告)号：US20120190191A1

    公开(公告)日：2012-07-26

    申请号：US13440704

    申请日：2012-04-05

    申请人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

    发明人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76849 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76865 ,  H01L21/76883

    摘要： An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.

    摘要翻译： 集成电路包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的第一开口，第一开口中的第一扩散阻挡层，覆盖第一开口中的低k电介质层 开口，其中所述第一扩散阻挡层具有连接到侧壁部分的底部，并且其中所述侧壁部分具有靠近所述低k电介质层的顶表面的顶表面。 集成电路还包括填充第一开口的导电线，其中导电线具有比扩散阻挡层的侧壁部分的顶表面低的顶表面，以及导电线上的金属盖，并且仅在直接在 导线。