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公开(公告)号：US20170352704A1
公开(公告)日：2017-12-07
申请号：US15686389
申请日：2017-08-25
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege , Krishna K. Parat
IPC: H01L27/24 , H01L29/792 , H01L27/1158 , H01L27/11553 , H01L29/66 , H01L45/00 , H01L29/788
CPC classification number: H01L27/2454 , H01L27/11553 , H01L27/1158 , H01L27/2481 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L45/1608
Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.
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公开(公告)号：US20170110198A1
公开(公告)日：2017-04-20
申请号：US15393719
申请日：2016-12-29
Applicant: Micron Technology, Inc.
Inventor： Han Zhao , Akira Goda , Krishna K. Parat , Aurelio Giancarlo Mauri , Haitao Liu , Toru Tanzawa , Shigekazu Yamada , Koji Sakui
CPC classification number: G11C16/3459 , G11C8/08 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/32 , G11C16/3445 , G11C2213/71
Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.
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公开(公告)号：US20160372556A1
公开(公告)日：2016-12-22
申请号：US15255402
申请日：2016-09-02
Applicant: Micron Technology, Inc.
Inventor： Haitao Liu , Akira Goda , Chandra Mouli , Krishna K. Parat
IPC: H01L29/40 , H01L27/115
CPC classification number: H01L29/408 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/7889 , H01L29/7926
Abstract: Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.
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公开(公告)号：US20160307622A1
公开(公告)日：2016-10-20
申请号：US15189178
申请日：2016-06-22
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shyam Sunder Raghunathan , Pranav Kalavade , Krishna K. Parat , Charan Srinivasan
CPC classification number: G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3427
Abstract: Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a programming pulse to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the multi-step pass voltage to the plurality of memory cells selected for the programming operation, applying a particular voltage level to any data lines coupled to a first subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the multi-step pass voltage, and applying the particular voltage level to any data lines coupled to a second subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the multi-step pass voltage.
Abstract translation: 操作存储器的方法包括对选择用于编程操作的多个存储器单元施加多级通过电压，在将编程脉冲施加到编程操作所选择的多个存储器单元之后，施加特定步骤的电压电平 向被选择用于编程操作的多个存储器单元的多步通过电压，将特定电压电平施加到耦合到在应用编程操作之前被选择用于编程操作的多个存储器单元中的存储器单元的第一子集的任何数据线 多级通过电压的某一步骤的电压电平，并且将特定电压电平施加到仅在施加电压电平之后耦合到被选择用于编程操作的多个存储器单元的存储器单元的第二子集的任何数据线 多步通过电压的一定步骤。
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公开(公告)号：US20160225822A1
公开(公告)日：2016-08-04
申请号：US15095208
申请日：2016-04-11
Applicant: Micron Technology, Inc.
Inventor： Sanh D. Tang , Roger W. Lindsay , Krishna K. Parat
IPC: H01L27/24 , G11C13/00 , H01L45/00 , H01L27/115 , H01L23/528
CPC classification number: H01L27/11582 , G11C13/0007 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75 , H01L23/52 , H01L23/528 , H01L27/10 , H01L27/101 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/249 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.
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Patent Agency Ranking
公开(公告)号：US20160019949A1
公开(公告)日：2016-01-21
申请号：US14334946
申请日：2014-07-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shyam Sunder Raghunathan , Pranav Kalavade , Krishna K. Parat , Charan Srinivasan
CPC classification number: G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3427
Abstract: Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be programmed to a particular target data state of the memory, using program disturb to program cells of the memory selected to be programmed to target data states that are lower than the particular target data state while programming cells of the memory selected to be programmed to the particular target data state, and boosting a channel voltage for cells of the memory selected to be programmed to the target data states that are lower than the particular target data state. Boosting may include using a multi-step pass signal.
Abstract translation: 提供了用于编程具有多级通过信号的存储器的存储器和方法。 一种方法包括将选择要编程的存储器的单元编程为存储器的特定目标数据状态，使用程序干扰来编程选择要编程的存储器的单元，以在编程期间将目标数据状态低于特定目标数据状态 将存储器的单元选择为被编程到特定目标数据状态，以及将选择要编程的存储器的单元的通道电压提升到低于特定目标数据状态的目标数据状态。 升压可能包括使用多步通过信号。
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公开(公告)号：US08767467B2
公开(公告)日：2014-07-01
申请号：US13970055
申请日：2013-08-19
Applicant: Micron Technology, Inc.
Inventor： Krishna K. Parat , Akira Goda , Koichi Kawal , Brian J. Soderling , Jeremy Binfet , Arnaud A. Furnemont , Tejas Krishnamohan , Tyson M. Stichka , Giuseppina Puzzilli
IPC: G11C16/04
CPC classification number: G11C29/765 , G11C11/5628 , G11C16/0483 , G11C16/16 , G11C16/349 , G11C29/789
Abstract: Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.
Abstract translation: 公开了存储器件和方法，包括涉及擦除存储器单元块的方法。 在擦除块之后，并且在块的后续编程之前，基于选择栅晶体管上的电荷积累来确定块中的多个不良串。 如果坏字符串的数量超过阈值，则该块将从使用中退出。 公开了另外的实施例。
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公开(公告)号：US11923289B2
公开(公告)日：2024-03-05
申请号：US17837923
申请日：2022-06-10
Applicant: Micron Technology, Inc.
Inventor： Sanh D. Tang , Roger W. Lindsay , Krishna K. Parat
IPC: H01L23/52 , G11C13/00 , H01L23/528 , H01L27/10 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35 , H10B63/00 , H10N70/00
CPC classification number: H01L23/52 , G11C13/0007 , H01L23/528 , H01L27/10 , H01L27/101 , H10B41/27 , H10B43/27 , H10B43/35 , H10B63/845 , H10N70/8822 , H10N70/8825 , H10N70/8828 , H10N70/8833 , H10N70/8836 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75 , H01L2924/0002 , H10B41/35 , H10N70/882 , H10N70/883 , H01L2924/0002 , H01L2924/00
Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.
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公开(公告)号：US11653494B2
公开(公告)日：2023-05-16
申请号：US16725139
申请日：2019-12-23
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege , Krishna K. Parat , Luan C. Tran , Meng-Wei Kuo , Yushi Hu
IPC: H01L27/11524 , H01L27/1157 , H01L27/11582 , H01L27/11556 , H01L21/822 , H01L27/11578 , H01L27/11529 , H01L27/1158
CPC classification number: H01L27/11524 , H01L27/1157 , H01L27/11556 , H01L27/11582 , H01L21/8221 , H01L27/1158 , H01L27/11529 , H01L27/11578
Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.
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公开(公告)号：US20220302015A1
公开(公告)日：2022-09-22
申请号：US17837923
申请日：2022-06-10
Applicant: Micron Technology, Inc.
Inventor： Sanh D. Tang , Roger W. Lindsay , Krishna K. Parat
IPC: H01L23/52 , H01L27/10 , G11C13/00 , H01L23/528 , H01L27/11556 , H01L27/11582 , H01L27/24 , H01L45/00 , H01L27/1157
Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.
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