公开(公告)号：US10062679B2

公开(公告)日：2018-08-28

申请号：US15847493

申请日：2017-12-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michel Koopmans

IPC: H01L21/68 ,  H01L21/78 ,  H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L21/78 ,  H01L22/14 ,  H01L24/80 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68354 ,  H01L2221/68395 ,  H01L2224/80006 ,  H01L2224/80203 ,  H01L2224/95001

Abstract: Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.

公开(公告)号：US20170336470A1

公开(公告)日：2017-11-23

申请号：US15660387

申请日：2017-07-26

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans ,  James M. Derderian

IPC: G01R31/28 ,  G01R1/073

CPC classification number: G01R31/2887 ,  G01R1/07307 ,  G01R31/2884

Abstract: Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. The substrate may comprise a semiconductor wafer or wafer segment and, if the latter, multiple segments may be received in recesses in a fixture. Testing may be effected using a probe card, a bond head carrying conductive pins, or through conductors carried by the fixture.

公开(公告)号：US09768147B2

公开(公告)日：2017-09-19

申请号：US14171169

申请日：2014-02-03

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans

IPC: H01L29/06 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/06102 ,  H01L2224/06519 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17519 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/00012

Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

公开(公告)号：US09733304B2

公开(公告)日：2017-08-15

申请号：US14495025

申请日：2014-09-24

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans ,  James M. Derderian

IPC: G01R31/28 ,  G01R1/073

CPC classification number: G01R31/2887 ,  G01R1/07307 ,  G01R31/2884

Abstract: Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. The substrate may comprise a semiconductor wafer or wafer segment and, if the latter, multiple segments may be received in recesses in a fixture. Testing may be effected using a probe card, a bond head carrying conductive pins, or through conductors carried by the fixture.

公开(公告)号：US09711494B2

公开(公告)日：2017-07-18

申请号：US14600976

申请日：2015-01-20

Applicant: Micron Technology, Inc.

Inventor： Luke G. England ,  Paul A. Silvestri ,  Michel Koopmans

IPC: H01L21/00 ,  H01L23/00 ,  H05K1/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/544 ,  H01L25/065 ,  H01L25/18 ,  H01L21/78 ,  H01L23/31 ,  H01L21/66 ,  H01L21/683

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/14 ,  H01L22/20 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/544 ,  H01L24/89 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54433 ,  H01L2224/16145 ,  H01L2224/80203 ,  H01L2224/80815 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.

公开(公告)号：US20160084905A1

公开(公告)日：2016-03-24

申请号：US14495025

申请日：2014-09-24

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans ,  James M. Derderian

IPC: G01R31/28 ,  G01R1/073 ,  G01R1/04

CPC classification number: G01R31/2887 ,  G01R1/07307 ,  G01R31/2884

Abstract: Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. The substrate may comprise a semiconductor wafer or wafer segment and, if the latter, multiple segments may be received in recesses in a fixture. Testing may be effected using a probe card, a bond head carrying conductive pins, or through conductors carried by the fixture.

Abstract translation: 用于测试包括管芯堆叠的半导体器件的设备，该设备包括其表面中具有凹穴阵列的衬底，其布置成对应于从待测试的半导体器件突出的导电元件。 凹穴包括导电接触件，导线延伸到导电焊盘，其可被配置为测试焊盘，跳线焊盘，边缘连接或接触焊盘。 衬底可以包括半导体晶片或晶片段，并且如果后者，多个段可以被容纳在固定装置中的凹槽中。 可以使用探针卡，承载导电针的接合头或通过固定器承载的导体进行测试。

公开(公告)号：US09269700B2

公开(公告)日：2016-02-23

申请号：US14231101

申请日：2014-03-31

Applicant: Micron Technology, Inc.

Inventor： Michel Koopmans ,  Shijian Luo ,  David R. Hembree

IPC: H01L23/02 ,  H01L25/18 ,  H01L23/34 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5226 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15156 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/01047

Abstract: Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a stack of semiconductor dies and a thermally conductive casing at least partially enclosing the stack of semiconductor dies within an enclosure. A package substrate carries the thermally conductive casing, and an interposer is disposed between the thermally conductive casing and the stack of semiconductor dies. A peripheral portion of the interposer extends laterally beyond the stack of semiconductor dies and is coupled to a plurality of conductive members interposed between the peripheral portion and the package substrate.

Abstract translation: 本文公开了具有改进的热性能和相关联的系统和方法的堆叠的半导体管芯组件。 在一个实施例中，半导体管芯组件可以包括半导体管芯堆叠和至少部分地围绕外壳内的半导体管芯堆叠的导热外壳。 封装衬底承载导热壳体，并且插入件设置在导热壳体和半导体管芯堆叠之间。 插入器的周边部分横向延伸超过半导体管芯堆叠，并且被连接到插入在周边部分和封装衬底之间的多个导电构件。

公开(公告)号：US08828798B2

公开(公告)日：2014-09-09

申请号：US14029187

申请日：2013-09-17

Applicant: Micron Technology, Inc.

Inventor： Luke G. England ,  Paul A. Silvestri ,  Michel Koopmans

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/66 ,  H01L21/44 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L21/683 ,  H01L25/18 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L22/10 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05655 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00

Abstract: Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.

Abstract translation: 制造多模组件的方法，其包括在其上没有集成电路并且具有多个垂直堆叠的骰子的晶片片段，其上通过导电通孔，所得到的多骰子组件和包括这种多模组件的半导体器件电连接。 晶片段可用作散热器，以增强在所得到的多模组件中从堆叠的骰子的热传递。 芯片堆叠在基底晶片上的晶片级制造，晶片段和管芯堆叠至少在至少外围封装之后被分割。

公开(公告)号：US11004494B2

公开(公告)日：2021-05-11

申请号：US16267087

申请日：2019-02-04

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kuo-Chen Wang ,  Martin C. Roberts ,  Diem Thy N. Tran ,  Hideki Gomi ,  Fredrick D. Fishburn ,  Srinivas Pulugurtha ,  Michel Koopmans ,  Eiji Hasunuma

IPC: G11C11/24 ,  G11C11/402 ,  H01L27/108 ,  G11C5/06 ,  G11C11/4097 ,  G11C5/02 ,  G11C8/14

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

公开(公告)号：US10461059B2

公开(公告)日：2019-10-29

申请号：US15007615

申请日：2016-01-27

Applicant: Micron Technology, Inc.

Inventor： Michel Koopmans ,  Shijian Luo ,  David R. Hembree

IPC: H01L23/02 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/373 ,  H01L23/522 ,  H01L23/367 ,  H01L23/498

Abstract: Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a stack of semiconductor dies and a thermally conductive casing at least partially enclosing the stack of semiconductor dies within an enclosure. A package substrate carries the thermally conductive casing, and an interposer is disposed between the thermally conductive casing and the stack of semiconductor dies. A peripheral portion of the interposer extends laterally beyond the stack of semiconductor dies and is coupled to a plurality of conductive members interposed between the peripheral portion and the package substrate.