公开(公告)号：US09468098B2

公开(公告)日：2016-10-11

申请号：US14220913

申请日：2014-03-20

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Jonghae Kim ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Robert Paul Mikulka

IPC: H01L23/538 ,  H05K1/11 ,  H05K1/03 ,  H05K1/18 ,  H05K3/30 ,  H05K3/40 ,  H01L23/48 ,  H01L23/64 ,  H05K1/02 ,  H05K3/36 ,  H05K1/14 ,  H05K1/16 ,  H05K3/34

CPC classification number: H05K3/303 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/19101 ,  H05K1/0243 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/141 ,  H05K1/144 ,  H05K1/165 ,  H05K1/18 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4007 ,  H05K3/4015 ,  H05K2201/1003 ,  H05K2201/10477 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/041 ,  H05K2203/1316 ,  Y10T29/4902 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: Systems and methods relate to a semiconductor package comprising a first substrate or a 2D passive-on-glass (POG) structure with a passive component and a first set of one or more package pads formed on a face of a glass substrate. The semiconductor package also includes a second or laminate substrate with a second set of one or more package pads formed on a face of the second or laminate substrate. Solder balls are dropped, configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the first substrate or the 2D POG structure is placed face-up on the face of the second or laminate substrate. A printed circuit board (PCB) can be coupled to a bottom side of the second or laminate substrate.

Abstract translation: 系统和方法涉及包括第一衬底或2D无源玻璃（POG）结构的半导体封装，其具有无源部件和形成在玻璃衬底的表面上的一个或多个封装焊盘的第一组。 半导体封装还包括具有第二组一个或多个封装焊盘的第二或层压衬底，其形成在第二层压衬底的表面上。 焊球被落下，被配置为使第一组一个或多个封装焊盘与第二组一个或多个封装焊盘接触，其中第一基板或2D POG结构朝上放置在第二或层压板的表面上 基质。 印刷电路板（PCB）可以耦合到第二或层压基板的底侧。

公开(公告)号：US09401689B2

公开(公告)日：2016-07-26

申请号：US13887568

申请日：2013-05-06

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Daeik D. Kim ,  Je-Hsiung Lan ,  Jonghae Kim ,  Mario Francisco Velez ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46

Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

公开(公告)号：US20160204758A1

公开(公告)日：2016-07-14

申请号：US15079789

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Daeik D. Kim ,  Je-Hsiung Lan ,  Jonghae Kim ,  Mario Francisco Velez ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46 ,  H03H7/01 ,  H03H3/00

CPC classification number: H03H7/461 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  Y10T29/49016

Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

Abstract translation: 公开了三维（3D）集成电路（IC）（3DIC）中的可调谐双工器。 在一个实施例中，可调谐双工器可以通过在双工器中提供变容二极管或可变电感器之一来形成。 可变电抗器或可变电感器的可变特性允许调谐双工器中的陷波，以便选择频带停止以消除期望频率处的谐波以及控制通带的截止频率。 通过将双工器的元件堆叠成三维空间是保守的，并且可以使用各种变容二极管和电感器。

公开(公告)号：US09384883B2

公开(公告)日：2016-07-05

申请号：US14155172

申请日：2014-01-14

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Jonghae Kim ,  Chengjie Zuo ,  Mario Francisco Velez ,  Changhan Hobie Yun

IPC: H01F27/28 ,  H01F41/00 ,  H01F17/00

CPC classification number: H01F41/041 ,  H01F27/2804 ,  H01F41/00 ,  H01F2017/0086 ,  H01F2027/2809 ,  H01L2924/0002 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A 3D nested transformer includes a substrate having a set of through substrate vias daisy chained together with a set of traces. At least some of the through substrate vias have first and second conductive regions. The set of traces also includes a first set of traces coupling together at least some of the first conductive regions of the through substrate vias, and a second set of traces coupling together at least some of the second conductive regions of the through substrate vias.

Abstract translation: 3D嵌套变压器包括具有与一组迹线菊花链连接的一组通过衬底通孔的衬底。 至少一些直通衬底通孔具有第一和第二导电区域。 该组迹线还包括将至少一些贯穿衬底通孔的第一导电区域耦合在一起的第一组迹线，以及将至少一些第二导电区域连接在一起的穿过衬底通孔的第二组迹线。

公开(公告)号：US09368566B2

公开(公告)日：2016-06-14

申请号：US14334521

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Jong-Hoon Lee ,  Young Kyu Song ,  Daeik Daniel Kim ,  Jung Ho Yoon ,  Uei-Ming Jow ,  Mario Francisco Velez ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L28/40 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

Abstract translation: 一些特征涉及包括衬底，第一管芯，第一封装层，第一再分配部分，第二管芯，第二封装层和第二封装层的集成器件（例如，封装封装（PoP）器件） 第二再分配部分。 基板包括第一表面和第二表面。 基板包括电容器。 第一管芯耦合到衬底的第一表面。 第一封装层封装第一裸片。 第一再分配部分耦合到第一封装。 第二管芯耦合到衬底的第二表面。 第二封装层封装第二管芯。 第二再分配部分耦合到第二封装层。

公开(公告)号：US09355967B2

公开(公告)日：2016-05-31

申请号：US13946135

申请日：2013-07-19

Applicant: QUALCOMM Incorporated

Inventor： Daeik D. Kim ,  Je-Hsiung Lan ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  Changhan Yun

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/02 ,  G06F17/50

CPC classification number: H01L23/562 ,  G06F17/5081 ,  G06F2217/80 ,  H01L21/02005 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00

Abstract: An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage prior to the device being detached from another device.

Abstract translation: 一种装置包括包括至少一层的装置。 所述至少一个层包括设备间应力补偿模式，其被配置为在所述设备从另一设备分离之前减少设备间翘曲的量。

公开(公告)号：US09343399B2

公开(公告)日：2016-05-17

申请号：US14149530

申请日：2014-01-07

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Jonghae Kim ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Niranjan Sunil Mudakatte

IPC: H01L21/02 ,  H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01L27/01 ,  H01L27/08 ,  H01L49/02

CPC classification number: H01L23/49822 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second conductive layer. The integrated circuit device also includes a first conductive stack including a third conductive layer coupled to a portion of the second conductive layer with a first via. The integrated circuit device further includes a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate. The integrated circuit device also includes a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer.

Abstract translation: 集成电路器件包括衬底，以及在衬底上的包括第一导电层和第二导电层的第一层间电介质层。 集成电路器件还包括第一导电叠层，其包括用第一通孔耦合到第二导电层的一部分的第三导电层。 集成电路器件还包括第二导电叠层，其包括直接位于与衬底隔离的第三导电层的一部分上的第四导电层。 集成电路器件还包括围绕第三导电层和第四导电层的第二层间介质层。

公开(公告)号：US09203373B2

公开(公告)日：2015-12-01

申请号：US13798733

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Mario Francisco Velez ,  Je-Hsiung Lan ,  Daeik D. Kim ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46 ,  H03H3/00 ,  H05K1/16 ,  H01L23/64 ,  H03H1/00 ,  H01L23/15 ,  H01L23/498 ,  H03H7/01 ,  H01F17/00 ,  H01L23/48 ,  H01L23/522 ,  H05K1/02 ,  H05K1/03 ,  H01L23/66

CPC classification number: H03H7/461 ,  H01F2017/0026 ,  H01F2017/004 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/64 ,  H01L23/66 ,  H01L2924/0002 ,  H03H3/00 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/1791 ,  H03H7/463 ,  H03H2001/0021 ,  H05K1/0233 ,  H05K1/0306 ,  H05K1/165 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2201/10015 ,  H05K2201/10098 ,  Y10T29/49128 ,  H01L2924/00

Abstract: A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate.

Abstract translation: 双工器包括具有一组通过衬底通孔的衬底。 双工器还包括在衬底的第一表面上的第一组迹线。 第一迹线耦合到贯穿衬底通孔。 双工器还包括与第一表面相对的在衬底的第二表面上的第二组迹线。 第二迹线耦合到该组通过衬底通孔的相对端。 贯通衬底通孔和迹线也作为3D电感器工作。 双工器还包括由基板支撑的电容器。

公开(公告)号：US20150215026A1

公开(公告)日：2015-07-30

申请号：US14684072

申请日：2015-04-10

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Changhan Hobie Yun ,  Chi Shun Lo ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H04B7/08 ,  H04B1/18

CPC classification number: H04B7/0805 ,  H04B1/005 ,  H04B1/16 ,  H04B1/18 ,  H04B7/0825

Abstract: A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.

Abstract translation: 分集接收机交换机包括被配置为与收发机通信的至少一个第二级交换机。 分集接收机交换机还可以包括耦合在分集接收机天线和第二级交换机之间的至少一个第一级交换机。 第一级开关可以被配置为处理与第二级开关不同的功率量。 分集接收器开关可以包括被配置为与收发器通信的一组第二级交换机。 第一级开关可以被配置为处理比第二级开关组中的每个开关更多的功率。 或者，分集接收器开关包括耦合在分集接收器天线和第二级开关之间的一组第一级开关。 第二级开关可以被配置为处理比每个第一级开关更多的功率。

公开(公告)号：US20150180437A1

公开(公告)日：2015-06-25

申请号：US14177620

申请日：2014-02-11

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Mario Francisco Velez ,  Jonghae Kim ,  Daeik Daniel Kim ,  Changhan Hobie Yun

IPC: H03H7/01

CPC classification number: H03H7/0115 ,  H01F27/2866 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48464 ,  Y10T29/417 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An inductor is provided on a substrate that includes a capacitor. The inductor comprises a series of wire loops. An end of the wire loop is wire bonded to the capacitor.

Abstract translation: 在包括电容器的基板上设置电感器。 电感器包括一系列线圈。 导线环的末端引线接合到电容器。