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公开(公告)号：US08999764B2
公开(公告)日：2015-04-07
申请号：US11836819
申请日：2007-08-10
IPC分类号： H01L21/00 , H01L23/532 , H01L23/556
CPC分类号： H01L23/5329 , H01L23/556 , H01L2924/0002 , Y10S438/958 , Y10S438/967 , H01L2924/00
摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.
摘要翻译： 公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。 一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。 另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。 电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。
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公开(公告)号：US08546961B2
公开(公告)日：2013-10-01
申请号：US12987202
申请日：2011-01-10
申请人： Mukta G. Farooq , Troy L. Graves-Abe , Robert Hannon , Emily R. Kinser , William F. Landers , Kevin S. Petrarca , Richard P. Volant , Kevin R. Winstel
发明人： Mukta G. Farooq , Troy L. Graves-Abe , Robert Hannon , Emily R. Kinser , William F. Landers , Kevin S. Petrarca , Richard P. Volant , Kevin R. Winstel
IPC分类号： H01L23/544 , H01L21/02
CPC分类号： H01L21/76898 , H01L21/8221 , H01L23/544 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2223/54426 , H01L2224/29187 , H01L2224/2919 , H01L2224/32145 , H01L2224/8385 , H01L2224/83896 , H01L2224/9202 , H01L2224/94 , H01L2225/06541 , H01L2225/06593 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2224/83
摘要： Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.
摘要翻译： 公开了包括对准标记的结构和在三维（3D）结构中形成对准标记的方法）。 该方法包括在第一半导体衬底的第一表面中形成孔; 将第一半导体衬底的第一表面接合到第二半导体衬底的第一表面; 在第一半导体衬底的第二表面上使第一半导体薄化以提供孔和第一半导体衬底之间的光学对比度; 以及使用所述孔将所述第一半导体衬底的所述第二表面上的特征对准为至少一个对准标记。
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公开(公告)号：US20110095435A1
公开(公告)日：2011-04-28
申请号：US12607098
申请日：2009-10-28
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage. A method of fabricating such a TSV structure is also described.
摘要翻译： 硅通孔（TSV）结构在硅衬底内形成独特的同轴或三轴互连。 TSV结构设置有两个或更多个与另一个绝缘的独立电导体和与衬底绝缘的独立电导体。 电导体可以连接到不同的电压或接地，使得可以将TSV结构作为同轴或三轴装置进行操作。 使用各种绝缘材料的多层可用作绝缘体，其中根据介电性能，填充性能，界面粘合性，CTE匹配等来选择层。 TSV结构克服了外绝缘层中可能导致泄漏的缺陷。 还描述了制造这种TSV结构的方法。
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公开(公告)号：US07816248B2
公开(公告)日：2010-10-19
申请号：US12138482
申请日：2008-06-13
IPC分类号： H01L21/44
CPC分类号： H01L24/10 , H01L24/13 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05026 , H01L2224/05027 , H01L2224/05085 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/13 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well.
摘要翻译： 公开了线焊料连接器的远端的实施例以及形成连接器的方法，其消除了使用铝，保护了球限制冶金（BLM）层的完整性，并且通过并入薄的保形膜来促进BLM层的粘附 导电衬里进入焊接接头结构。 该导电衬里以通孔填充物的顶部涂覆任何刻痕，以便产生用于BLM沉积的均匀表面，从而保护BLM层的完整性。 衬垫还涂覆在其中形成BLM层的阱的电介质侧壁，以便增强BLM层与阱的粘合性。
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公开(公告)号：US20080248643A1
公开(公告)日：2008-10-09
申请号：US12138482
申请日：2008-06-13
IPC分类号： H01L21/44
CPC分类号： H01L24/10 , H01L24/13 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05026 , H01L2224/05027 , H01L2224/05085 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/13 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well.
摘要翻译： 公开了线焊料连接器的远端的实施例以及形成连接器的方法，其消除了使用铝，保护了球限制冶金（BLM）层的完整性，并且通过并入薄的保形膜来促进BLM层的粘附 导电衬里进入焊接接头结构。 该导电衬里以通孔填充物的顶部涂覆任何刻痕，以便产生用于BLM沉积的均匀表面，从而保护BLM层的完整性。 衬垫还涂覆在其中形成BLM层的阱的电介质侧壁，以便增强BLM层与阱的粘合性。
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公开(公告)号：US08455356B2
公开(公告)日：2013-06-04
申请号：US12690948
申请日：2010-01-21
IPC分类号： H01L25/11
CPC分类号： H01L21/76879 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L24/16 , H01L24/29 , H01L24/82 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/29 , H01L2224/29298 , H01L2224/9202 , H01L2224/92144 , H01L2225/06541 , H01L2225/06575 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/12042 , H01L2924/14 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2224/05552 , H01L2924/00
摘要： A microelectronic assembly and related method of forming a through hole extending through a first wafer and a second wafer are provided. The first and second wafer have confronting faces and metallic features at the faces which are joined together to assemble the first and second wafers. A hole can be etched downwardly through the first wafer until a gap is partially exposed between the confronting faces of the first and second wafers. The hole can have a first wall extending in a vertical direction, and a second wall sloping inwardly from the first wall to an inner opening through which the interfacial gap is exposed. Material of the first or second wafers exposed within the hole can then be sputtered such that at least some of the sputtered material deposits onto at least one of the exposed confronting faces of the first and second wafers and provides a wall between the confronting faces. The method can include resuming etching the hole so as to extend the first wall fully through the first wafer, the wall between the wafers and into the second wafer, such that the wall of the hole extends continuously from the first wafer into the second wafer. An electrically conductive through silicon via can then be formed extending through the first wafer, the wall between the wafers and into the second wafer.
摘要翻译： 提供了形成延伸穿过第一晶片和第二晶片的通孔的微电子组件和相关方法。 第一和第二晶片在面处具有面对面和金属特征，这些面被连接在一起以组装第一和第二晶片。 孔可以向下蚀刻通过第一晶片，直到在第一和第二晶片的相对面之间部分露出间隙。 该孔可以具有在垂直方向上延伸的第一壁，以及从第一壁向内倾斜到内部开口的第二壁，界面间隙暴露在该内部开口中。 然后可以溅射暴露在孔内的第一或第二晶片的材料，使得至少一些溅射的材料沉积到第一和第二晶片的暴露的相对面中的至少一个上，并且在相对面之间提供壁。 该方法可以包括恢复蚀刻孔，以便将第一壁完全延伸穿过第一晶片，晶片之间的壁和第二晶片，使得孔的壁从第一晶片连续延伸到第二晶片。 然后可以形成延伸穿过第一晶片，晶片之间的壁并进入第二晶片的导电的硅通孔。
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公开(公告)号：US08394715B2
公开(公告)日：2013-03-12
申请号：US13495092
申请日：2012-06-13
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage.
摘要翻译： 一种制造在硅衬底内形成独特的同轴或三轴互连的穿硅通孔（TSV）结构的方法。 TSV结构设置有两个或更多个与另一个绝缘的独立电导体和与衬底绝缘的独立电导体。 电导体可以连接到不同的电压或接地，使得可以将TSV结构作为同轴或三轴装置进行操作。 使用各种绝缘材料的多层可用作绝缘体，其中根据介电性能，填充性能，界面粘合性，CTE匹配等来选择层。 TSV结构克服了外绝缘层中可能导致泄漏的缺陷。
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公开(公告)号：US20120161300A1
公开(公告)日：2012-06-28
申请号：US13409643
申请日：2012-03-01
IPC分类号： H01L23/552
CPC分类号： H01L23/5329 , H01L23/556 , H01L2924/0002 , Y10S438/958 , Y10S438/967 , H01L2924/00
摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.
摘要翻译： 公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。 一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。 另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。 电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。
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公开(公告)号：US20120135564A1
公开(公告)日：2012-05-31
申请号：US13361057
申请日：2012-01-30
IPC分类号： H01L21/60
CPC分类号： H01L24/16 , H01L24/11 , H01L24/13 , H01L24/81 , H01L2224/05001 , H01L2224/05023 , H01L2224/05568 , H01L2224/10126 , H01L2224/1147 , H01L2224/1148 , H01L2224/1191 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/81801 , H01L2924/00013 , H01L2924/01005 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/15787 , H01L2224/29099 , H01L2924/00 , H01L2224/05541 , H01L2224/05005
摘要： A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.
摘要翻译： 一种方法产生一种结构，其包括通过柱和开口连接到集成电路芯片的载体。 因此，在这种结构中，至少一个导电柱与集成电路芯片的表面延伸一段距离或高度，并且阻挡层围绕导电柱的下部，使得阻挡层覆盖柱的高度的至少一部分 最接近芯片表面。 载体中至少有一个开口足够大以容纳导电柱和屏障，并且导电柱和屏障位于开口中。 在开口的底部使用焊料将导电柱连接到开口的底部。 屏障防止焊料接触由屏障保护的导电柱的部分。
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30.发明申请METHOD OF FORMING A MULTI-CHIP STACKED STRUCTURE INCLUDING A THIN INTERPOSER CHIP HAVING A FACE-TO-BACK BONDING WITH ANOTHER CHIP 有权形成多芯片堆叠结构的方法，其中包括具有另一个芯片的面对背结合的薄间隙芯片公开(公告)号：US20110237026A1
公开(公告)日：2011-09-29
申请号：US12731487
申请日：2010-03-25
IPC分类号： H01L21/50
CPC分类号： H01L21/6835 , H01L23/3128 , H01L25/50 , H01L2221/68327 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01322 , H01L2924/1305 , H01L2924/00
摘要： A temporary substrate having an array of first solder pads is bonded to the front side of a first substrate by reflowing an array of first solder balls. The first substrate is thinned by removing the back side, and an array of second solder pads is formed on the back side surface of the first substrate. The assembly of the first substrate and the temporary substrate is diced to form a plurality of stacks, each including an assembly of a first semiconductor chip and a handle portion. A second semiconductor chip is bonded to an assembly through an array of the second solder balls. The handle portion is removed from each assembly by reflowing the array of the first solder balls, while the array of the second solder balls does not reflow. The assembly is subsequently mounted on a packaging substrate employing the array of the first solder balls.
摘要翻译： 具有第一焊盘的阵列的临时衬底通过回流第一焊球的阵列而结合到第一衬底的正面。 通过去除背面而使第一衬底变薄，并且在第一衬底的背侧表面上形成第二焊盘阵列。 第一基板和临时基板的组装被切割以形成多个堆叠，每个堆叠包括第一半导体芯片和手柄部分的组件。 第二半导体芯片通过第二焊球的阵列结合到组件。 通过回流第一焊球的阵列，第二焊球的阵列不会回流，从每个组件移除把手部分。 随后使用第一焊球的阵列将组件安装在包装衬底上。
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