公开(公告)号：US20180294221A1

公开(公告)日：2018-10-11

申请号：US15858529

申请日：2017-12-29

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/585 ,  H01L28/10

Abstract: A semiconductor device includes: a plurality of first wires formed in a first layer and indicating fixed potentials; and an inductor formed in a second layer stacked on the first layer, and wiring widths of the first wires located within a range of a formation region of the inductor in a plan view among the plurality of first wires are formed narrower than wiring widths of the first wires located outside the range of the formation region of the inductor.

公开(公告)号：US09536828B2

公开(公告)日：2017-01-03

申请号：US14651643

申请日：2012-12-19

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida ,  Hirokazu Nagase ,  Takuo Funaya

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/64 ,  H01L25/065 ,  H01L27/06 ,  H01L23/495 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/5227 ,  H01L23/49575 ,  H01L23/528 ,  H01L23/645 ,  H01L23/66 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L27/0688 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: On a semiconductor substrate, coils CL5 and CL6 and pads PD5, PD6, and PD7 are formed. The coil CL5 and the coil CL6 are electrically connected in series between the pad PD5 and the pad PD6, and the pad PD7 is electrically connected between the coil CL5 and the coil CL6. The coil magnetically coupled to the coil CL5 is formed just below the coil CL5, the coil magnetically coupled to the coil CL6 is formed just below the coil CL6, and they are connected in series. When a current is flowed in the coils connected in series formed just below the coils CL5 and CL6, directions of induction current flowing in the coils CL5 and CL6 are opposed to each other in the coils CL5 and CL6.

Abstract translation: 在半导体衬底上形成线圈CL5和CL6以及焊盘PD5，PD6和PD7。 线圈CL5和线圈CL6串联地电连接在焊盘PD5和焊盘PD6之间，并且焊盘PD7电连接在线圈CL5和线圈CL6之间。 磁耦合到线圈CL5的线圈形成在线圈CL5的正下方，与线圈CL6磁性耦合的线圈形成在线圈CL6的正下方，并且它们串联连接。 当线圈CL5和CL6正下方的串联连接的线圈中流过电流时，线圈CL5和CL6中流过的感应电流的方向在线圈CL5和CL6中彼此相对。

公开(公告)号：US09013025B2

公开(公告)日：2015-04-21

申请号：US14148893

申请日：2014-01-07

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida ,  Yasutaka Nakashiba

IPC: H01L27/08 ,  H01F21/12 ,  H01L49/02 ,  H01L23/64

CPC classification number: H01F21/12 ,  H01F21/10 ,  H01L23/5227 ,  H01L23/645 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor device includes an insulation layer, an inductor, fixed electrodes, and a movable electrode. The inductor is formed on the insulation layer. The fixed electrodes are provided in positions which do not overlap with the inductor in a planar view. The movable electrode overlaps with the inductor and the fixed electrodes in the planar view, and is separated from the inductor and the fixed electrodes. Further, the movable electrode includes first openings.

Abstract translation: 电感器件包括绝缘层，电感器，固定电极和可动电极。 电感器形成在绝缘层上。 固定电极设置在平面图中不与电感器重叠的位置。 可动电极在平面图中与电感器和固定电极重叠，并且与电感器和固定电极分离。 此外，可动电极包括第一开口。

公开(公告)号：US20150061645A1

公开(公告)日：2015-03-05

申请号：US14477538

申请日：2014-09-04

Applicant: Renesas Electronics Corporation

Inventor： Takatsugu Nemoto ,  Yasutaka Nakashiba ,  Takasuke Hashimoto ,  Shinichi Uchida

IPC: G01R1/20 ,  G01R19/00

CPC classification number: G01R19/0092 ,  G01R1/203 ,  G01R15/181

Abstract: This invention provides a sensor device at reduced cost. The sensor device includes a printed circuit board, a first terminal, a second terminal, an interconnect line, and a semiconductor device. The first terminal and second terminal are provided on the printed circuit board and coupled to a power line. The second terminal is coupled to a downstream part of the power line with respect to the first terminal. The interconnect line is disposed on the printed circuit board to couple the first terminal and second terminal to each other. In other words, the interconnect line is coupled to the power line in parallel. The semiconductor device is mounted on the printed circuit board and includes an interconnect layer and an inductor formed in the interconnect layer.

Abstract translation: 本发明以更低的成本提供传感器装置。 传感器装置包括印刷电路板，第一端子，第二端子，互连线和半导体器件。 第一端子和第二端子设置在印刷电路板上并耦合到电力线。 第二端子相对于第一端子耦合到电力线的下游部分。 互连线布置在印刷电路板上以将第一端子和第二端子彼此耦合。 换句话说，互连线并联耦合到电力线。 半导体器件安装在印刷电路板上，并且包括形成在互连层中的互连层和电感器。

公开(公告)号：US11901288B2

公开(公告)日：2024-02-13

申请号：US16924968

申请日：2020-07-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba ,  Shinichi Uchida

IPC: H03F3/187 ,  H01L23/522 ,  H01L49/02 ,  H03M1/12 ,  H03F3/04

CPC classification number: H01L23/5227 ,  H01L23/5226 ,  H01L28/10 ,  H03F3/04 ,  H03M1/12

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element, and a multilayer wiring. The semiconductor element is formed on the semiconductor substrate. The multilayer wiring includes a wiring electrically connected with the semiconductor element, and a first inductor. The multilayer wiring is formed on the semiconductor substrate such that the multilayer wiring covers the semiconductor element. The first inductor is formed such that the first inductor electrically isolated from the wiring and is magnetically connected with the wiring.

公开(公告)号：US10818591B2

公开(公告)日：2020-10-27

申请号：US15953872

申请日：2018-04-16

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida ,  Yasutaka Nakashiba ,  Tetsuya Iida ,  Shinichi Kuwabara

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L25/065 ,  H01L23/532 ,  H04B5/00

Abstract: A method of manufacturing a semiconductor device includes a step of: patterning a conductive film formed over an interlayer insulating film so as to form a coil and a conductive pattern in the same layer, and then forming unevennesses on a surface of the interlayer insulating film by etching a portion of the interlayer insulating film with using the coil and the conductive pattern as a mask.

公开(公告)号：US20200013716A1

公开(公告)日：2020-01-09

申请号：US16577228

申请日：2019-09-20

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida

IPC: H01L23/522 ,  H01L49/02

Abstract: A semiconductor device includes a plurality of first wires formed in a first layer, a plurality of second wires formed to intersect the plurality of first wires in a second layer stacked on the first layer, a plurality of first vias formed at intersections of the plurality of first wires and the plurality of second wires, and an inductor formed in a third layer stacked on the first layer and the second layer.

公开(公告)号：US10115684B2

公开(公告)日：2018-10-30

申请号：US15424059

申请日：2017-02-03

Applicant: Renesas Electronics Corporation

Inventor： Shinpei Watanabe ,  Shinichi Uchida ,  Tadashi Maeda ,  Kazuo Henmi

IPC: H01L23/64 ,  H01F38/14 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L49/02

Abstract: A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.

公开(公告)号：US20170148751A1

公开(公告)日：2017-05-25

申请号：US15424059

申请日：2017-02-03

Applicant: Renesas Electronics Corporation

Inventor： Shinpei WATANABE ,  Shinichi Uchida ,  Tadashi Maeda ,  Kazuo Henmi

IPC: H01L23/64 ,  H01F38/14 ,  H01L23/495 ,  H01L23/31 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L23/645 ,  H01F17/0013 ,  H01F38/14 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/162 ,  H01L28/10 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06527 ,  H01L2924/13055 ,  H01L2924/181 ,  H04B5/0031 ,  H04B5/0081 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/01014

Abstract: A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.

公开(公告)号：US09466591B2

公开(公告)日：2016-10-11

申请号：US14989661

申请日：2016-01-06

Applicant: Renesas Electronics Corporation

Inventor： Shinpei Watanabe ,  Shinichi Uchida ,  Tadashi Maeda ,  Shigeru Tanaka

IPC: H01L49/02 ,  H01L25/065 ,  H04B5/00 ,  H01L23/522 ,  H01L23/64 ,  H01L27/06 ,  H01L23/495 ,  H01L23/00 ,  H01L23/62 ,  H01L23/31 ,  H01L27/092

CPC classification number: H01L25/0657 ,  H01L23/3185 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/62 ,  H01L23/645 ,  H01L24/32 ,  H01L24/73 ,  H01L27/0617 ,  H01L27/0922 ,  H01L28/10 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2924/1206 ,  H01L2924/181 ,  H01L2924/19042 ,  H04B5/005 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a first semiconductor chip that includes a first main surface, a first inductor formed on the first main surface, and a first external connection terminal formed on the first main surface; a second semiconductor chip that includes a second main surface, a second inductor formed on the second main surface, a second external connection terminal formed on the second main surface; and a first insulating film that is located between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip overlap each other such that the first main surface and the second main face each other, the semiconductor device includes a facing region in which the first semiconductor chip and the second semiconductor chip overlap each other when seen in a plan view.

Abstract translation: 半导体器件包括：第一半导体芯片，包括第一主表面，形成在第一主表面上的第一电感器和形成在第一主表面上的第一外部连接端子; 第二半导体芯片，包括第二主表面，形成在第二主表面上的第二电感器，形成在第二主表面上的第二外部连接端子; 以及位于所述第一半导体芯片和所述第二半导体芯片之间的第一绝缘膜，其中所述第一半导体芯片和所述第二半导体芯片彼此重叠，使得所述第一主表面和所述第二主面彼此相对，所述半导体器件包括 当在平面图中看到第一半导体芯片和第二半导体芯片彼此重叠时的面对区域。