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    Microstructure modification in copper interconnect structure
    25.
    发明授权
    Microstructure modification in copper interconnect structure 失效
    铜互连结构中的微结构改性

    公开(公告)号：US08008199B2

    公开(公告)日：2011-08-30

    申请号：US12869113

    申请日：2010-08-26

    申请人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

    发明人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

    IPC分类号： H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/76877 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.

    摘要翻译： 为了改变铜线和通孔的微观结构，将钴添加到铜种子层，铜镀层或铜覆盖层。 钴可以是铜 - 钴合金的形式或作为非常薄的钴层。 本发明金属互连结构中竹结构中晶界的结构关闭了铜晶界扩散。 晶粒生长后的金属互连结构的组成含有约1ppm至约10原子浓度的钴。 晶粒边界从铜 - 钴合金线的顶表面延伸到铜 - 钴合金线的底表面，并且与任何其它晶界分开大于铜 - 钴合金线的宽度的距离。

    MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURE
    26.
    发明申请
    MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURE 失效
    铜互连结构中的微观结构修改

    公开(公告)号：US20100323517A1

    公开(公告)日：2010-12-23

    申请号：US12869113

    申请日：2010-08-26

    申请人： Brett C. Baker-O'Neal ,  Cyril Cabral, JR. ,  Qiang Huang ,  Kenneth P. Rodbell

    发明人： Brett C. Baker-O'Neal ,  Cyril Cabral, JR. ,  Qiang Huang ,  Kenneth P. Rodbell

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76877 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.

    摘要翻译： 为了改变铜线和通孔的微观结构，将钴添加到铜种子层，铜镀层或铜覆盖层。 钴可以是铜 - 钴合金的形式或作为非常薄的钴层。 本发明金属互连结构中竹结构中晶界的结构关闭了铜晶界扩散。 晶粒生长后的金属互连结构的组成含有约1ppm至约10原子浓度的钴。 晶粒边界从铜 - 钴合金线的顶表面延伸到铜 - 钴合金线的底表面，并且与任何其它晶界分开大于铜 - 钴合金线的宽度的距离。

    Microstructure modification in copper interconnect structure
    27.
    发明授权
    Microstructure modification in copper interconnect structure 有权
    铜互连结构中的微结构改性

    公开(公告)号：US07843063B2

    公开(公告)日：2010-11-30

    申请号：US12031103

    申请日：2008-02-14

    申请人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

    发明人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/76877 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.

    摘要翻译： 为了改变铜线和通孔的微观结构，将钴添加到铜种子层，铜镀层或铜覆盖层。 钴可以是铜 - 钴合金的形式或作为非常薄的钴层。 本发明金属互连结构中竹结构中晶界的结构关闭了铜晶界扩散。 晶粒生长后的金属互连结构的组成含有约1ppm至约10原子浓度的钴。 晶粒边界从铜 - 钴合金线的顶表面延伸到铜 - 钴合金线的底表面，并且与任何其它晶界分开大于铜 - 钴合金线的宽度的距离。

    Method for plating copper conductors and devices formed
    29.
    发明授权
    Method for plating copper conductors and devices formed 有权
    电镀铜导体和器件的方法

    公开(公告)号：US06344129B1

    公开(公告)日：2002-02-05

    申请号：US09418197

    申请日：1999-10-13

    申请人： Kenneth P. Rodbell ,  Panayotis C. Andricacos ,  Cyril Cabral, Jr. ,  Lynne M. Gignac ,  Cyprian E. Uzoh ,  Peter S. Locke

    发明人： Kenneth P. Rodbell ,  Panayotis C. Andricacos ,  Cyril Cabral, Jr. ,  Lynne M. Gignac ,  Cyprian E. Uzoh ,  Peter S. Locke

    IPC分类号： C25D500

    CPC分类号： C25D5/10 ,  C25D3/38 ,  C25D5/00 ,  C25D7/123 ,  C25D21/02 ,  H05K3/423

    摘要： A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as {fraction (1/10)}. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process. These parameters include the bath temperature, the bath agitation, the additive concentration in the plating bath, the plating current density utilized, the deposition rate of the copper film and the total thickness of the copper film deposited.

    摘要翻译： 公开了一种在电子基板上镀铜导体的方法和形成的器件。 在该方法中，首先提供填充有保持在约0℃至约18℃之间的温度的电镀溶液的电镀铜浴。 然后将浸在电镀溶液中的电子基板上的铜层以单步骤或双步沉积工艺进行镀覆。 双步沉积方法更适合于在具有大纵横比的特征中沉积铜导体，例如双镶嵌结构中的通孔，其直径/深度的纵横比大于1/3或高达{分数（ 1/10）}。 各种电镀参数用于在单步沉积或双步沉积工艺中提供短电阻瞬变。 这些参数包括浴温度，浴液搅拌，镀浴中的添加剂浓度，所用的电镀电流密度，铜膜的沉积速率和沉积的铜膜的总厚度。

    Ionizing radiation blocking in IC chip to reduce soft errors
    30.
    发明授权
    Ionizing radiation blocking in IC chip to reduce soft errors 有权
    IC芯片中的电离辐射阻断减少软错误

    公开(公告)号：US08999764B2

    公开(公告)日：2015-04-07

    申请号：US11836819

    申请日：2007-08-10

    申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

    发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

    IPC分类号： H01L21/00 ,  H01L23/532 ,  H01L23/556

    CPC分类号： H01L23/5329 ,  H01L23/556 ,  H01L2924/0002 ,  Y10S438/958 ,  Y10S438/967 ,  H01L2924/00

    摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

    摘要翻译： 公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。 一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。 另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。 电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。