公开(公告)号：US20070275565A1

公开(公告)日：2007-11-29

申请号：US11838942

申请日：2007-08-15

申请人： Edward Cooney ,  Robert Geffken ,  Vincent McGahay ,  William Motsiff ,  Mark Murray ,  Amanda Piper ,  Anthony Stamper ,  David Thomas ,  Elizabeth Webster

发明人： Edward Cooney ,  Robert Geffken ,  Vincent McGahay ,  William Motsiff ,  Mark Murray ,  Amanda Piper ,  Anthony Stamper ,  David Thomas ,  Elizabeth Webster

IPC分类号： H01L21/311

CPC分类号： H01L23/53238 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76838 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for semiconductor structure includes a plurality of adjacent wiring levels, conductors within each of the wiring levels, and liners at least partially surrounding each of the conductors. The liners of adjacent wiring levels are made of different materials which have different etching characteristics and are selectively etchable with respect to one another. The liners can be tantalum, tungsten, etc. The liners surround at least three sides of the conductors. Each of the wiring levels has a first insulator layer which has a first dielectric material. The liners and the conductors are positioned within the first dielectric material. A second insulator layer has a second dielectric material over the first insulator layer. The first dielectric material has a lower dielectric constant than the second dielectric material. The first dielectric material can be silicon dioxide, fluorinated silicon dioxide (FSD), microporous glasses, etc. The second dielectric material can be one of nitrides, oxides, tantalum, tungsten, etc.

摘要翻译： 用于半导体结构的方法和结构包括多个相邻布线层，每个布线层内的导体和至少部分地围绕每个导体的衬垫。 相邻布线层的衬垫由具有不同蚀刻特性并且可相对于彼此选择性地蚀刻的不同材料制成。 衬垫可以是钽，钨等。衬里围绕导体的至少三个侧面。 每个布线层具有第一绝缘体层，其具有第一介电材料。 衬垫和导体位于第一介电材料内。 第二绝缘体层在第一绝缘体层上具有第二电介质材料。 第一电介质材料具有比第二电介质材料低的介电常数。 第一介电材料可以是二氧化硅，氟化二氧化硅（FSD），微孔玻璃等。第二介电材料可以是氮化物，氧化物，钽，钨等中的一种。

公开(公告)号：US20070228570A1

公开(公告)日：2007-10-04

申请号：US11763135

申请日：2007-06-14

申请人： Christos Dimitrakopoulos ,  Stephen Gates ,  Vincent McGahay ,  Sanjay Mehta

发明人： Christos Dimitrakopoulos ,  Stephen Gates ,  Vincent McGahay ,  Sanjay Mehta

IPC分类号： H01L23/532

CPC分类号： H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.

摘要翻译： 本发明涉及改进单镶嵌型或双镶嵌型互连结构的制造方法，其中在制造之后金属线之间没有硬掩模保持或导电性问题。 本发明的方法包括化学机械抛光和紫外线曝光或化学修复处理的至少步骤，这些步骤提高了形成的互连结构的可靠性。 本发明还涉及一种互连结构，其包括SiCOH型的多孔超低k电介质，其中其表面层被修饰以形成具有密度梯度和C含量梯度的梯度层。

公开(公告)号：US20070152332A1

公开(公告)日：2007-07-05

申请号：US11306596

申请日：2006-01-04

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Vincent McGahay ,  Anthony Stamper ,  Kunal Vaed ,  Richard Volant

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Vincent McGahay ,  Anthony Stamper ,  Kunal Vaed ,  Richard Volant

IPC分类号： H01L21/44

CPC分类号： H01L21/76838 ,  H01L23/5223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to integrated circuits that comprise via-level wirings and/or devices. Specifically, an integrate circuit of the present invention comprises a first line level and a second line level spaced apart from each other, with a via level therebetween. The first and second line levels both comprise metal wirings and/or electronic devices. The via level comprises at least one metal via that extends therethrough to electrically connect the first line level with the second line level. Further, the via level comprises at least one via-level metal wiring and/or electronic device.

摘要翻译： 本发明涉及包括通孔级布线和/或器件的集成电路。 具体而言，本发明的集成电路包括彼此间隔开的第一线路电平和第二线路电平，其间具有通路电平。 第一和第二线路级均包括金属布线和/或电子设备。 通孔级包括至少一个穿过其中的金属通孔，以将第一线路电平与第二线路电平电连接。 此外，通孔电平包括至少一个通孔级金属布线和/或电子器件。

公开(公告)号：US20060091559A1

公开(公告)日：2006-05-04

申请号：US10981233

申请日：2004-11-04

申请人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

发明人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

IPC分类号： H01L21/4763 ,  H01L23/52 ,  H01L21/31

CPC分类号： H01L21/3148 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

公开(公告)号：US06972209B2

公开(公告)日：2005-12-06

申请号：US10306534

申请日：2002-11-27

申请人： Birendra N. Agarwala ,  Conrad A. Barile ,  Hormazdyar M. Dalal ,  Brett H. Engle ,  Michael Lane ,  Ernest Levine ,  Xiao Hu Liu ,  Vincent McGahay ,  John F. McGrath ,  Conal E. Murray ,  Jawahar P. Nayak ,  Du B. Nguyen ,  Hazara S. Rathore ,  Thomas M. Shaw

发明人： Birendra N. Agarwala ,  Conrad A. Barile ,  Hormazdyar M. Dalal ,  Brett H. Engle ,  Michael Lane ,  Ernest Levine ,  Xiao Hu Liu ,  Vincent McGahay ,  John F. McGrath ,  Conal E. Murray ,  Jawahar P. Nayak ,  Du B. Nguyen ,  Hazara S. Rathore ,  Thomas M. Shaw

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/00

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/24917 ,  H01L2924/00

摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

摘要翻译： 一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。 多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。 在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织 互连级别，从而增加互连级别之间堆叠通孔的灵活性。

公开(公告)号：US06486557B1

公开(公告)日：2002-11-26

申请号：US09515110

申请日：2000-02-29

申请人： Charles R. Davis ,  Daniel Charles Edelstein ,  John C. Hay ,  Jeffrey C. Hedrick ,  Christopher Jahnes ,  Vincent McGahay ,  Henry A. Nye, III

发明人： Charles R. Davis ,  Daniel Charles Edelstein ,  John C. Hay ,  Jeffrey C. Hedrick ,  Christopher Jahnes ,  Vincent McGahay ,  Henry A. Nye, III

IPC分类号： H01L2348

CPC分类号： H01L21/76808 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-level, coplanar copper damascene interconnect structure on an integrated circuit chip includes a first planar interconnect layer on an integrated circuit substrate and having plural line conductors separated by a dielectric material having a relatively low dielectric constant and a relatively low elastic modulus. A second planar interconnect layer on the first planar interconnect layer comprises a dielectric film having an elastic modulus higher than in the first planar interconnect layer and conductive vias therethrough. The vias are selectively in contact with the line conductors. A third planar interconnect layer on the second planar interconnect layer has plural line conductors separated by the dielectric material and selectively in contact with the vias.

摘要翻译： 集成电路芯片上的多层共面铜镶嵌互连结构包括在集成电路基板上的第一平面互连层，并且具有由具有相对较低的介电常数和相对低的弹性模量的介电材料隔开的多个线导体。 第一平面互连层上的第二平面互连层包括具有高于第一平面互连层的弹性模量和通过其的导电通孔的电介质膜。 通孔选择性地与线路导体接触。 第二平面互连层上的第三平面互连层具有被电介质材料隔开并选择性地与通孔接触的多个线导体。

公开(公告)号：US07972965B2

公开(公告)日：2011-07-05

申请号：US11862706

申请日：2007-09-27

申请人： Edward C. Cooney, III ,  Vincent McGahay ,  Thomas M. Shaw ,  Anthony K. Stamper ,  Matthew E. Colburn

发明人： Edward C. Cooney, III ,  Vincent McGahay ,  Thomas M. Shaw ,  Anthony K. Stamper ,  Matthew E. Colburn

IPC分类号： H01L21/311

CPC分类号： H01L21/76829 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/78

摘要： The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.

摘要翻译： 本发明涉及使用图案化粗糙化改善电介质的界面粘附的方法。 可以通过增加材料之间的界面的粗糙度来实现层和基底之间的改善的粘附强度。 粗糙度可能包括任何干扰通常平滑的表面，如凹槽，凹痕，孔，沟槽等。 可以通过在衬底的表面上沉积材料作为掩模，然后使用蚀刻工艺来引起粗糙度来实现界面上的粗加工。 用作掩模的材料允许蚀刻在以常规光掩模和光刻实现的规模以下的精细或次微小尺度上发生，以实现所需的图案粗糙化。 然后将另一种材料沉积在基底的粗糙表面上，填充粗加工并粘附到基底上。

公开(公告)号：US07303994B2

公开(公告)日：2007-12-04

申请号：US10710034

申请日：2004-06-14

申请人： Edward C. Cooney, III ,  Vincent McGahay ,  Thomas M Shaw ,  Anthony K. Stamper ,  Matthew E. Colburn

发明人： Edward C. Cooney, III ,  Vincent McGahay ,  Thomas M Shaw ,  Anthony K. Stamper ,  Matthew E. Colburn

IPC分类号： H01L21/302

CPC分类号： H01L21/76829 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/78

摘要： The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.

摘要翻译： 本发明涉及使用图案化粗糙化改善电介质的界面粘附的方法。 可以通过增加材料之间的界面的粗糙度来实现层和基底之间的改善的粘附强度。 粗糙度可能包括任何干扰通常平滑的表面，如凹槽，凹痕，孔，沟槽等。 可以通过在衬底的表面上沉积材料作为掩模，然后使用蚀刻工艺来引起粗糙度来实现界面上的粗加工。 用作掩模的材料允许蚀刻在以常规光掩模和光刻实现的规模以下的精细或次微小尺度上发生，以实现所需的图案粗糙化。 然后将另一种材料沉积在基底的粗糙表面上，填充粗加工并粘附到基底上。

公开(公告)号：US20060189133A1

公开(公告)日：2006-08-24

申请号：US11063152

申请日：2005-02-22

申请人： Christos Dimitrakopoulos ,  Stephen Gates ,  Vincent McGahay ,  Sanjay Mehta

发明人： Christos Dimitrakopoulos ,  Stephen Gates ,  Vincent McGahay ,  Sanjay Mehta

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.

摘要翻译： 本发明涉及改进单镶嵌型或双镶嵌型互连结构的制造方法，其中在制造之后金属线之间没有硬掩模保持或导电性问题。 本发明的方法包括化学机械抛光和紫外线曝光或化学修复处理的至少步骤，这些步骤提高了形成的互连结构的可靠性。 本发明还涉及一种互连结构，其包括SiCOH型的多孔超低k电介质，其中其表面层被修饰以形成具有密度梯度和C含量梯度的梯度层。

公开(公告)号：US20050277266A1

公开(公告)日：2005-12-15

申请号：US10710034

申请日：2004-06-14

申请人： Edward Cooney ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper ,  Matthew Colburn

发明人： Edward Cooney ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper ,  Matthew Colburn

IPC分类号： C23C14/00 ,  C23C14/32 ,  H01L21/30 ,  H01L21/302 ,  H01L21/311 ,  H01L21/46 ,  H01L21/461 ,  H01L21/768 ,  H01L21/78

CPC分类号： H01L21/76829 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/78

摘要： The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.

摘要翻译： 本发明涉及使用图案化粗糙化改善电介质的界面粘附的方法。 可以通过增加材料之间的界面的粗糙度来实现层和基底之间的改善的粘附强度。 粗糙度可能包括任何干扰通常平滑的表面，如凹槽，凹痕，孔，沟槽等。 可以通过在衬底的表面上沉积材料作为掩模，然后使用蚀刻工艺来引起粗糙度来实现界面上的粗加工。 用作掩模的材料允许蚀刻在以常规光掩模和光刻实现的规模以下的精细或次微小尺度上发生，以实现所需的图案粗糙化。 然后将另一种材料沉积在基底的粗糙表面上，填充粗加工并粘附到基底上。