公开(公告)号：US12113050B2

公开(公告)日：2024-10-08

申请号：US17552614

申请日：2021-12-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Sick Park ,  Un-Byoung Kang ,  Jongho Lee ,  Teak Hoon Lee

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/06051 ,  H01L2224/061 ,  H01L2224/06519 ,  H01L2224/16147 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/3841

Abstract: Disclosed is a semiconductor package with increased thermal radiation efficiency, which includes: a first die having signal and dummy regions and including first vias in the signal region, a second die on the first die and including second vias in the signal region, first die pads on a top surface of the first die and coupled to the first vias, first connection terminals on the first die pads which couple the second vias to the first vias, second die pads in the dummy region and on the top surface of the first die, and second connection terminals on the second die pads and electrically insulated from the first vias and the second vias. Each of the second die pads has a rectangular planar shape whose major axis is provided along a direction that leads away from the signal region.

公开(公告)号：US20240237349A1

公开(公告)日：2024-07-11

申请号：US18464348

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Un-Byoung Kang ,  Jumyong Park ,  Dongjoon Oh ,  Hyunchul Jung ,  Sanghoo Cho

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/528 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L23/5283 ,  H01L25/0652 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06506

Abstract: A three-dimensional semiconductor memory device may include a bottom structure and a top structure thereon. The bottom structure may include a semiconductor substrate including a cell array region and a connection region extending therefrom, and a first stack including first gate electrodes and first interlayer insulating layers alternately stacked on the semiconductor substrate. The top structure may include a second stack including second gate electrodes and second interlayer insulating layers alternately stacked on the first stack. Respective lengths of the first gate electrodes in a second direction may decrease as a distance in a first direction increases, and respective lengths of the second gate electrodes in the second direction may increase as a distance in the first direction increases. The first direction may be perpendicular to a bottom surface of the semiconductor substrate, and the second direction may be parallel to the bottom surface of the semiconductor substrate.

公开(公告)号：US12014977B2

公开(公告)日：2024-06-18

申请号：US18199824

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Seok Hong ,  Dongwoo Kim ,  Hyunah Kim ,  Un-Byoung Kang ,  Chungsun Lee

IPC: H01L21/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822

Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.

公开(公告)号：US20240162184A1

公开(公告)日：2024-05-16

申请号：US18337113

申请日：2023-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Sick Park ,  Un-Byoung Kang ,  Min Soo Kim ,  Seon Gyo Kim

IPC: H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L24/33 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/3003 ,  H01L2224/30505 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2924/0665 ,  H01L2924/067 ,  H01L2924/07025 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443

Abstract: A semiconductor package includes a first structure, a first semiconductor chip on the first structure, a first conductive pad on the first structure between the first structure and the first semiconductor chip, a second conductive pad on a lower surface of the first semiconductor chip and vertically overlapping the first conductive pad, a bump connecting the first conductive pad and the second conductive pad, a first adhesive layer surrounding at least a part of side walls of the bump and side walls of the first conductive pad, and a second adhesive layer surrounding at least a part of the side walls of the bump and side walls of the second conductive pad, the second adhesive layer including a material different from the first adhesive layer, wherein a horizontal width of the first adhesive layer is smaller than a horizontal width of the second adhesive layer.

公开(公告)号：US11688679B2

公开(公告)日：2023-06-27

申请号：US17324569

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Seok Hong ,  Dongwoo Kim ,  Hyunah Kim ,  Un-Byoung Kang ,  Chungsun Lee

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822

Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.

公开(公告)号：US11616039B2

公开(公告)日：2023-03-28

申请号：US17220299

申请日：2021-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Sick Park ,  Un-Byoung Kang ,  Seon Gyo Kim ,  Joon Ho Jun

IPC: H01L23/48 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor package including a first stack; a plurality of TSVs passing through the first stack; a second stack on the first stack and including a second surface facing a first surface of the first stack; a first pad on the first stack and in contact with the TSVs; a second pad on the second stack; a bump connecting the first and second pads; a first redundancy pad on the first surface of the first stack, spaced apart from the first pad, and not in contact with the TSVs; a second redundancy pad on the second surface of the second stack and spaced apart from the second pad; and a redundancy bump connecting the first redundancy pad and the second redundancy pad, wherein the first pad and first redundancy pad are electrically connected to each other, and the second pad and second redundancy pad are electrically connected to each other.

公开(公告)号：US11594499B2

公开(公告)日：2023-02-28

申请号：US17203007

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon Ko ,  Un-Byoung Kang ,  Jaekyung Yoo ,  Teak Hoon Lee

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/13

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

公开(公告)号：US11018026B2

公开(公告)日：2021-05-25

申请号：US16699283

申请日：2019-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Un-Byoung Kang ,  Tae-Je Cho ,  Hyuek-Jae Lee ,  Cha-Jea Jo

IPC: H05K1/11 ,  H05K1/18 ,  H01L21/48 ,  H05K3/46 ,  C23C18/00 ,  H01L23/433 ,  H01L23/498 ,  B05D1/00 ,  B05D1/32 ,  B05D1/38 ,  B05D3/02 ,  B05D7/00 ,  C23C14/02 ,  C23C14/04 ,  C23C14/06 ,  C23C14/20 ,  C23C14/34 ,  C23C14/58 ,  C23C18/38 ,  H01L23/00 ,  H01L25/03 ,  H01L23/473 ,  H01L23/538 ,  H01L25/065 ,  H05K1/14

Abstract: A semiconductor package includes: a plurality of unit redistribution layers vertically stacked, each including: a first polymer layer having a first via hole pattern; a second polymer layer formed on the first polymer layer, and having a redistribution pattern on the first polymer layer and a second via hole pattern in the first via hole pattern; a seed layer covering sidewalls and bottom surfaces of the redistribution pattern and the second via hole pattern; a conductive via plug formed in the second via hole pattern; and a conductive redistribution line formed in the redistribution pattern; a connection terminal disposed on a bottom surface of a lowermost unit redistribution layer and electrically connected to the conductive via plug; a semiconductor device mounted on the unit redistribution layers with a conductive terminal interposed therebetween. Upper surfaces of the second polymer layer, the conductive redistribution line and the conductive via plug are substantially coplanar.

公开(公告)号：US10262971B2

公开(公告)日：2019-04-16

申请号：US15469837

申请日：2017-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung Kang ,  Yungcheol Kong ,  Kyoungsei Choi

IPC: H01L25/04 ,  H01L23/49 ,  H01L23/528 ,  H01L27/146

Abstract: Provided are a stacked image sensor package and a packaging method thereof. A stacked image sensor package includes: a stacked image sensor in which a pixel array die and a logic die are stacked; a redistribution layer formed on one surface of the stacked image sensor, rerouting an input/output of the stacked image sensor, and including a first pad and a second pad; a memory die connected with the first pad of the redistribution layer and positioned on the stacked image sensor; and external connectors connected with the second pad, connecting the memory die and the stacked image sensor with an external device, and having the memory die positioned therebetween.

公开(公告)号：US08884421B2

公开(公告)日：2014-11-11

申请号：US14143178

申请日：2013-12-30

Applicant: Samsung Electronics Co., Ltd

Inventor： Un-Byoung Kang ,  Jong-Joo Lee ,  Yong-Hoon Kim ,  Tae-Hong Min

IPC: H01L23/02 ,  H01L23/367 ,  H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/49827 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.