公开(公告)号：US06287970B1

公开(公告)日：2001-09-11

申请号：US09370912

申请日：1999-08-06

申请人： Sailesh Mansinh Merchant ,  Sudhanshu Misra ,  William Michael Moller ,  Pradip Kumar Roy

发明人： Sailesh Mansinh Merchant ,  Sudhanshu Misra ,  William Michael Moller ,  Pradip Kumar Roy

IPC分类号： H01L2144

CPC分类号： H01L21/76877 ,  H01L21/321 ,  H01L21/76886

摘要： A method of making a semiconductor device includes the steps of forming an oxide layer adjacent a semiconductor substrate, etching trenches within the oxide layer, depositing a copper layer to at least fill the etched trenches, and forming a copper arsenate layer on the deposited copper layer. The copper arsenate layer is then chemically mechanically polished. The copper layer may be deposited by at least one of electrodeposition, electroplating and chemical vapor deposition. The copper arsenate layer on the surface of the deposited copper layer inhibits oxidation and corrosion and stabilizes the microstructure of the deposited copper layer to thereby eliminate a need to subsequently anneal the deposited copper layer.

摘要翻译： 制造半导体器件的方法包括以下步骤：在半导体衬底附近形成氧化物层，蚀刻氧化物层内的沟槽，沉积铜层以至少填充蚀刻的沟槽，以及在沉积的铜层上形成砷酸铜层 。 然后将砷酸铜层化学机械抛光。 可以通过电沉积，电镀和化学气相沉积中的至少一种来沉积铜层。 沉积的铜层表面上的砷酸铜层抑制氧化和腐蚀并稳定沉积的铜层的微观结构，从而不需要随后退火沉积的铜层。

公开(公告)号：US06235594B1

公开(公告)日：2001-05-22

申请号：US09340224

申请日：1999-06-25

申请人： Sailesh Mansinh Merchant ,  Pradip Kumar Roy

发明人： Sailesh Mansinh Merchant ,  Pradip Kumar Roy

IPC分类号： H01L21336

CPC分类号： H01L28/56 ,  H01L21/28194 ,  H01L27/1085 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： A method of fabricating an integrated circuit device includes forming a first metal oxide layer adjacent a semiconductor substrate. The first metal oxide layer may be formed of tantalum oxide, for example. A second metal oxide layer, which includes an oxide with a relatively high dielectric constant such as titanium oxide, zirconium oxide, or ruthenium oxide, is formed on the first metal oxide layer opposite the semiconductor substrate, and a metal nitride layer, such as titanium nitride, is formed on the metal oxide layer opposite the first metal oxide layer. The metal nitride layer includes a metal which is capable of reducing the metal oxide of the first metal oxide layer. Thus, the second metal oxide layer substantially blocks reduction of the metal oxide of the first metal oxide layer by the metal of the metal nitride layer.

摘要翻译： 制造集成电路器件的方法包括：形成与半导体衬底相邻的第一金属氧化物层。 第一金属氧化物层例如可以由氧化钽形成。 在与半导体衬底相对的第一金属氧化物层上形成第二金属氧化物层，其包含氧化钛，氧化锆或氧化钌等介电常数较高的氧化物，金属氮化物层如钛 在与第一金属氧化物层相对的金属氧化物层上形成氮化物。 金属氮化物层包括能够还原第一金属氧化物层的金属氧化物的金属。 因此，第二金属氧化物层通过金属氮化物层的金属基本上阻止第一金属氧化物层的金属氧化物的还原。

公开(公告)号：US06218255B1

公开(公告)日：2001-04-17

申请号：US09277778

申请日：1999-03-29

申请人： Larry Bruce Fritzinger ,  Nace Layadi ,  Sailesh Mansinh Merchant ,  Pradip Kumar Roy

发明人： Larry Bruce Fritzinger ,  Nace Layadi ,  Sailesh Mansinh Merchant ,  Pradip Kumar Roy

IPC分类号： H01L2120

CPC分类号： H01L28/60 ,  H01L21/3212 ,  H01L21/32136 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/75 ,  H01L28/90

摘要： The present invention provides a method for fabricating a capacitor, comprising the steps of forming a trench in a substrate, forming a layer of a first material selected from the group consisting of titanium and titanium nitride in the trench, filling the trench with a conductive material to form a conductive plug, planarizing the substrate, patterning the substrate to partially expose the first material and to create a top portion and a bottom portion to the plug, wherein the bottom portion is in the substrate, and removing the first material from the top portion of the plug.

摘要翻译： 本发明提供一种制造电容器的方法，包括以下步骤：在衬底中形成沟槽，在沟槽中形成从由钛和氮化钛组成的组中选择的第一材料的层，用导电材料填充沟槽 以形成导电插塞，平坦化基板，图案化基板以部分地暴露第一材料并且产生到插头的顶部部分和底部部分，其中底部部分在基板中，并且从顶部移除第一材料 插头的一部分。

公开(公告)号：US06180518B2

公开(公告)日：2001-01-30

申请号：US09430226

申请日：1999-10-29

申请人： Nace Layadi ,  Sailesh Mansinh Merchant ,  Simon John Molloy ,  Pradip Kumar Roy

发明人： Nace Layadi ,  Sailesh Mansinh Merchant ,  Simon John Molloy ,  Pradip Kumar Roy

IPC分类号： H01L214763

CPC分类号： H01L21/02063 ,  H01L21/31138 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76831

摘要： A method for making a semiconductor device includes the steps of forming a first conductive layer adjacent a substrate, forming an etch stop layer on the conductive layer, and forming a dielectric layer on the etch stop layer. The dielectric layer includes a material having a low dielectric constant, and a via is formed through the dielectric layer to expose the etch stop layer at the bottom, with porous sidewalls being produced. The exposed etch stop layer is etched using an etchant that cooperates with etched material from the etch stop layer to form a polymeric layer to coat the porous sidewalls of the via. Since the etchant cooperates with the etched material from the etch stop layer to form the polymeric layer coating the porous sidewalls of the via, a separate coating layer deposition step is not required after the via is etched and cleaned. After the porous sidewalls have been coated and polymeric material has been etched from the bottom of the via, a barrier metal layer is formed on the polymeric layer, a seed layer is formed on the barrier metal layer, and a second conductive layer is formed on the seed layer contacting the first conductive layer in the via.

摘要翻译： 制造半导体器件的方法包括以下步骤：在衬底附近形成第一导电层，在导电层上形成蚀刻停止层，并在蚀刻停止层上形成介电层。 电介质层包括具有低介电常数的材料，并且通过介电层形成通孔以暴露底部的蚀刻停止层，产生多孔侧壁。 使用与蚀刻停止层的蚀刻材料配合的蚀刻剂来蚀刻暴露的蚀刻停止层，以形成聚合物层以涂覆通孔的多孔侧壁。 由于蚀刻剂与来自蚀刻停止层的蚀刻材料配合以形成涂覆通孔的多孔侧壁的聚合物层，在蚀刻和清洁通孔之后不需要单独的涂层沉积步骤。 在已经涂覆多孔侧壁并且已经从通孔的底部蚀刻聚合物材料之后，在聚合物层上形成阻挡金属层，在阻挡金属层上形成种子层，并且在第二导电层上形成第二导电层 种子层与通孔中的第一导电层接触。

公开(公告)号：US06169036A

公开(公告)日：2001-01-02

申请号：US09276034

申请日：1999-03-25

申请人： Siddhartha Bhowmik ,  Joseph William Buckfeller ,  G. Craig Clabough ,  Sailesh Mansinh Merchant

发明人： Siddhartha Bhowmik ,  Joseph William Buckfeller ,  G. Craig Clabough ,  Sailesh Mansinh Merchant

IPC分类号： H01L2100

CPC分类号： H01L21/02063 ,  H01L21/32136 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76838

摘要： A method is for cleaning via openings during manufacturing of integrated circuits. The method preferably comprises the steps of sputter cleaning the via opening at least once, and exposing the via opening to a reducing atmosphere at least once. The method may include alternatingly repeating the sputter cleaning and exposing steps. The step of sputter cleaning is preferably performed prior to the step of exposing, and a sputter cleaning may be performed after a last step of exposing the via opening to the reducing atmosphere. In one embodiment, the exposed metal portion comprises a metal compound, such as an oxide. Accordingly, the step of sputter cleaning removes at least a portion of the metal oxide, and the step of exposing comprises reducing at least a portion of the metal oxide. The invention is particularly applicable when the metal interconnection layer is a copper, as copper readily oxides at its exposed surface.

摘要翻译： 一种用于在集成电路制造期间通孔的清洁方法。 该方法优选地包括以下步骤：将通孔开口至少一次溅射清洗，并将通孔开至少一次暴露于还原气氛。 该方法可以包括交替重复溅射清洗和曝光步骤。 溅射清洗的步骤优选在曝光步骤之前进行，并且可以在将通孔打开至还原气氛的最后步骤之后进行溅射清洗。 在一个实施方案中，暴露的金属部分包括金属化合物，例如氧化物。 因此，溅射清洗的步骤除去至少一部分金属氧化物，并且曝光步骤包括还原金属氧化物的至少一部分。 当金属互连层是铜时，本发明特别适用，因为铜在其暴露的表面容易氧化。

公开(公告)号：US5807760A

公开(公告)日：1998-09-15

申请号：US706932

申请日：1996-09-03

申请人： Joseph William Buckfeller ,  Sailesh Chittipeddi ,  Sailesh Mansinh Merchant

发明人： Joseph William Buckfeller ,  Sailesh Chittipeddi ,  Sailesh Mansinh Merchant

IPC分类号： C23C14/34 ,  C23C14/50 ,  C23C14/54 ,  C23C16/12 ,  C23C16/46 ,  C23C16/50 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/283

CPC分类号： H01L21/2855 ,  C23C14/50 ,  C23C14/541 ,  H01L21/76877

摘要： A method of depositing aluminum or other metals so that vias are more completely filled is disclosed. The wafer or substrate is preheated to a temperature of approximately 200.degree. C. Then the wafer is placed in an ambient of approximately 350.degree. C. while metal deposition commences. The resulting metal layer has a gradually increasing grain size and exhibits improved via filling. Also disclosed is a method and apparatus (involving cooling of support structures) for deposition of an anti-reflective coating to prevent rainbowing or spiking of the coating into the underlying metal.

摘要翻译： 公开了一种沉积铝或其它金属使得通孔更完全填充的方法。 将晶片或衬底预热至约200℃的温度。然后将晶片置于约350℃的环境中，同时开始金属沉积。 所得到的金属层具有逐渐增加的晶粒尺寸并表现出改进的通孔填充。 还公开了一种方法和装置（包括冷却支撑结构），用于沉积防反射涂层，以防止涂层向底层金属中起彩虹或尖峰。

公开(公告)号：US07566964B2

公开(公告)日：2009-07-28

申请号：US10675258

申请日：2003-09-30

申请人： Seung H. Kang ,  Roland P. Krebs ,  Kurt George Steiner ,  Michael C. Ayukawa ,  Sailesh Mansinh Merchant

发明人： Seung H. Kang ,  Roland P. Krebs ,  Kurt George Steiner ,  Michael C. Ayukawa ,  Sailesh Mansinh Merchant

IPC分类号： H01L23/52

CPC分类号： H01L23/5286 ,  H01L23/53214 ,  H01L23/53228 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit device structure and a process for fabricating the structure wherein the power bus interconnect structure is formed in the aluminum pad or contact layer. An interconnect structure for interconnecting underlying levels of interconnect can also be formed in the aluminum pad layer.

摘要翻译： 集成电路器件结构和制造该结构的工艺，其中电源总线互连结构形成在铝焊盘或接触层中。 用于互连互连的下层的互连结构也可以形成在铝焊盘层中。

公开(公告)号：US07541238B2

公开(公告)日：2009-06-02

申请号：US11414902

申请日：2006-05-01

申请人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Kurt George Steiner ,  Susan Clay Vitkavage

发明人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Kurt George Steiner ,  Susan Clay Vitkavage

IPC分类号： H01L21/8238

CPC分类号： H01L24/10 ,  H01F41/041 ,  H01L23/5227 ,  H01L24/13 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  Y10T29/4902 ,  H01L2924/00 ,  H01L2224/48

摘要： An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.

摘要翻译： 在集成电路内形成的电感器和形成电感器的方法。 该电感器包括形成在第一金属化层中并被图案化并蚀刻成所需形状的铝的下层。 在一个实施例中，铝线包括螺旋形状。 根据镶嵌工艺，在覆盖铝线并且与其电接触的介电层中形成优选铜的导电流道。 铝线和导电流道配合形成电感器。 在另一个实施例中，铝线和导电流道以垂直间隔的方向形成，其中形成钨塞或导电通孔以提供电连接。 形成电感器的方法包括形成铝导线并在导线上形成导电流道。

公开(公告)号：US20090100668A1

公开(公告)日：2009-04-23

申请号：US12340813

申请日：2008-12-22

申请人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Kurt George Steiner ,  Susan Clay Vitkavage

发明人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Kurt George Steiner ,  Susan Clay Vitkavage

IPC分类号： H01F41/00

CPC分类号： H01L24/10 ,  H01F41/041 ,  H01L23/5227 ,  H01L24/13 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  Y10T29/4902 ,  H01L2924/00 ,  H01L2224/48

摘要： An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.

摘要翻译： 在集成电路内形成的电感器和形成电感器的方法。 该电感器包括形成在第一金属化层中并被图案化并蚀刻成所需形状的铝的下层。 在一个实施例中，铝线包括螺旋形状。 根据镶嵌工艺，在覆盖铝线并且与其电接触的介电层中形成优选铜的导电流道。 铝线和导电流道配合形成电感器。 在另一个实施例中，铝线和导电流道以垂直间隔的方向形成，其中形成钨塞或导电通孔以提供电连接。 形成电感器的方法包括形成铝导线并在导线上形成导电流道。

公开(公告)号：US06790757B1

公开(公告)日：2004-09-14

申请号：US09467253

申请日：1999-12-20

申请人： Sailesh Chittipeddi ,  Sailesh Mansinh Merchant

发明人： Sailesh Chittipeddi ,  Sailesh Mansinh Merchant

IPC分类号： H01L2144

CPC分类号： H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/04042 ,  H01L2224/05681 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45624 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/78301 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2224/85948 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01066 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/00 ,  H01L2224/48781 ,  H01L2224/48681 ,  H01L2224/45147 ,  H01L2924/00015 ,  H01L2924/013 ,  H01L2924/01006

摘要： The present invention uses wire bonding technology to bond interconnect materials that oxidize easily by using a wire with stable oxidation qualities. A passivation layer is formed on the semiconductor substrate to encapsulate the bonding pad made from the interconnect material such that the wire bonds with the passivation layer itself, not with the interconnect material. The passivation layer is selected to be a material that is metallurgically stable when bonded to the interconnect material. Since the wire is stable compared with the interconnect material, i.e., it does not readily corrode, a reliable mechanical and electrical connection is provided between the semiconductor device (interconnect material) and the wire, with the passivation layer disposed therebetween.

摘要翻译： 本发明使用引线接合技术，通过使用具有稳定的氧化特性的导线，可以容易地接合易氧化的互连材料。 在半导体衬底上形成钝化层以封装由互连材料制成的接合焊盘，使得引线与钝化层本身而不是与互连材料结合。 钝化层选择为当结合到互连材料时是冶金稳定的材料。 由于线与互连材料相比是稳定的，即不易腐蚀，所以在半导体器件（互连材料）和导线之间提供可靠的机械和电连接，其中钝化层位于它们之间。