公开(公告)号：US5553766A

公开(公告)日：1996-09-10

申请号：US342563

申请日：1994-11-21

申请人： Raymond A. Jackson ,  Kathleen A. Lidestri ,  David C. Linnell ,  Raj N. Master

发明人： Raymond A. Jackson ,  Kathleen A. Lidestri ,  David C. Linnell ,  Raj N. Master

IPC分类号： B23K1/018 ,  H05K13/04 ,  H05K3/34 ,  B23K3/00

CPC分类号： H05K13/0486 ,  B23K1/018 ,  B23K2201/40

摘要： Deformation of a lifting ring of bimetallic structure or memory metal is matched to a solder softening or melting temperature to apply forces to lift a chip from a supporting structure, such as a substrate or multi-chip module, only when the solder connections between the chip and the supporting structure are softened or melted. The temperature of the chip, module and solder connections there between is achieved in a commercially available box oven or belt furnace or the like and results in much reduced internal chip temperatures and thermal gradients within the chip as compared to known hot chip removal processes. Tensile and/or shear forces at solder connections and chip and substrate contacts are much reduced in comparison with known cold chip removal processes. Accordingly, the process is repeatable at will without significant damage to or alteration of electrical characteristics of the chip or substrate.

摘要翻译： 双金属结构或记忆金属的提升环的变形与焊料软化或熔化温度匹配，以施加力以从支撑结构（例如基板或多芯片模块）提升芯片，只有当芯片之间的焊料连接 支撑结构软化或熔化。 与市售的盒式炉或带式炉等相比，芯片，模块和焊料连接的温度是可以实现的，并且与已知的热切屑去除工艺相比，在芯片内的内部芯片温度和热梯度大大降低。 与已知的冷芯片去除工艺相比，焊料连接和芯片和基板触点处的拉伸和/或剪切力大大降低。 因此，该过程可以随意重复，而不会显着损坏或改变芯片或衬底的电特性。

公开(公告)号：US5153408A

公开(公告)日：1992-10-06

申请号：US607969

申请日：1990-10-31

申请人： Edward F. Handford ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  Raymond A. Jackson ,  Raj N. Master ,  Sudipta K. Ray ,  William E. Sablinski ,  Thomas A. Wassick

发明人： Edward F. Handford ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  Raymond A. Jackson ,  Raj N. Master ,  Sudipta K. Ray ,  William E. Sablinski ,  Thomas A. Wassick

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/498 ,  H01L23/52 ,  H01L23/525 ,  H01L23/538 ,  H05K3/00 ,  H05K3/02 ,  H05K3/22 ,  H05K3/34

CPC分类号： H01L21/76892 ,  H01L23/49866 ,  H01L23/525 ,  H05K3/225 ,  H01L2924/0002 ,  H05K2201/10181 ,  H05K2201/10234 ,  H05K2201/1028 ,  H05K2201/10287 ,  H05K2203/0769 ,  H05K2203/107 ,  H05K2203/121 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/0017 ,  H05K3/027 ,  H05K3/34 ,  Y10T29/49124

摘要： The present invention relates generally to a new method of repairing electrical lines, and more praticularly to repairing electrical lines having an open at the module level with devices in place. Various methods and processes are used to repair this open or defective portion in an electrical conductor line. It could be repaired by securing a jumper wire or nugget across the open or the repair could be made by a deposition process, which includes but is not limited to filling the open with a solder type material or inserting a solder coated electrical wire and heating the solder and allowing the solder to melt and repair the open. One of the attributes of this invention is the ability to repair on a substrate or module on which active components such as chips, and passive components such as pins, capacitors, etc. have been attached. The invention also allows repair of fine line patterns which are normally not repairable by conventional techniques.

摘要翻译： 本发明一般涉及一种修复电线的新方法，并且更具体地涉及在装置就位时修复在模块级具有开路的电线。 使用各种方法和过程来修复电导体线中的这个开路或有缺陷的部分。 它可以通过将跨接线或熔核固定在开口处进行修复，或者可以通过沉积工艺进行修复，该沉积工艺包括但不限于用焊料型材料填充开口或插入焊料涂覆的电线并加热 焊接并允许焊料熔化并修复开路。 本发明的一个特征是在其上附着有诸如引脚，电容器等的诸如芯片和无源部件的有源部件的基板或模块上进行修复的能力。 本发明还允许修复通常不能通过常规技术修复的细线图案。

公开(公告)号：US06812570B2

公开(公告)日：2004-11-02

申请号：US10184061

申请日：2002-06-28

申请人： Raj N. Master ,  Mohammad Zubair Khan ,  Maria Guardado ,  Charles Anderson

发明人： Raj N. Master ,  Mohammad Zubair Khan ,  Maria Guardado ,  Charles Anderson

IPC分类号： H01L2348

CPC分类号： H01L24/81 ,  H01L23/145 ,  H01L23/49883 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K3/3463 ,  Y10T29/49144 ,  Y10T428/24917

摘要： An organic carrier member for mounting a semiconductor device is provided that has a plurality of solder pads containing low amounts of tin and bismuth. Embodiments include a bismaleimide-triazine epoxy laminate having a plurality of solder pads on the surface thereof where the solder pads contain no more than about 20 weight percent tin and has a reflow temperature of no greater than about 270° C.

摘要翻译： 提供一种用于安装半导体器件的有机载体构件，其具有多个含有少量锡和铋的焊盘。 实施方案包括其表面上具有多个焊料垫的双马来酰亚胺 - 三嗪环氧层压板，其中焊盘含有不超过约20重量％的锡并具有不大于约270℃的回流温度。

公开(公告)号：US06709963B1

公开(公告)日：2004-03-23

申请号：US09617104

申请日：2000-07-14

申请人： Jonathan D. Halderman ,  Raj N. Master

发明人： Jonathan D. Halderman ,  Raj N. Master

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30107 ,  H05K3/3436 ,  H05K3/3489 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method and an apparatus are provided for selectively depositing flux on a plurality of flip-chip bumps arranged on a semiconductor chip by jet printing a flux pattern, which is substantially identical to the arrangement pattern of the flip-chip bumps. The flux pattern is determined by measuring the chip configuration and converting the configuration to computer-recognizable data. The converted chip configuration is stored in data storage, and a jet printing head prints the flux pattern based on the computer-recognizable data. A conveyance plate is provided to transport the semiconductor chip to a flux-deposition area below the jet printing head.

摘要翻译： 提供了一种方法和装置，用于通过喷射打印基本上与倒装芯片凸块的布置图案相同的磁通图案，在布置在半导体芯片上的多个倒装芯片凸块上选择性地沉积磁通。 通过测量芯片配置并将配置转换为计算机可识别的数据来确定通量模式。 转换的芯片配置存储在数据存储器中，并且喷墨打印头基于计算机可识别的数据打印通量图案。 提供传送板以将半导体芯片传送到喷墨打印头下方的助熔剂区域。

公开(公告)号：US06591992B1

公开(公告)日：2003-07-15

申请号：US10227382

申请日：2002-08-26

申请人： Ajit M. Dubey ,  Raj N. Master ,  Ong Ot ,  Chan Cs

发明人： Ajit M. Dubey ,  Raj N. Master ,  Ong Ot ,  Chan Cs

IPC分类号： A47F700

CPC分类号： H01L21/67333 ,  H01L21/67028 ,  H01L2221/68313

摘要： A boat for cleaning semiconductor packages, including cleaning ball grid array packages in centrifugal cleaners. The boat includes a bottom plate with receptacles for receiving semiconductor packages and a top plate having through holes, where each through hole is smaller than the receptacle with which it corresponds in the bottom plate. An alignment mechanism ensures that the top plate is aligned with the bottom plate in a manner that results in each through hole being positioned directly over a respective one of the receptacles. An attachment mechanism releasably attaches the top plate to the bottom plate in a co-planar relationship that results in the presence of a vertical space between the two plates.

公开(公告)号：US06536649B1

公开(公告)日：2003-03-25

申请号：US09627437

申请日：2000-07-28

申请人： Raj N. Master ,  Jonathan D. Halderman

发明人： Raj N. Master ,  Jonathan D. Halderman

IPC分类号： B23R3704

CPC分类号： H01L21/67253

摘要： Residue contaminates semiconductor devices during processing in a furnace. Residue contamination is prevented by removing the residue before it builds up to a point where it can contaminate semiconductor devices. Residue build-up is monitored using a residue build-up monitoring device mounted on the furnace exhaust stack. When residue build-up reaches a predetermined level a signal is generated by the residue build-up monitoring device notifying technicians that furnace cleaning is required.

摘要翻译： 残渣在炉中加工期间污染半导体器件。 通过在残留物积聚到可能污染半导体器件的点之前去除残留物来防止残留污染。 使用安装在炉排气堆上的残渣积聚监测装置来监测残留物积聚。 当残渣累积达到预定水平时，残留物积聚监测装置产生信号，通知技术人员需要进行炉清洗。

公开(公告)号：US06409070B1

公开(公告)日：2002-06-25

申请号：US09663939

申请日：2000-09-18

申请人： Raj N. Master ,  Mohammad Z. Khan ,  Maria G. Guardado ,  Diong Hing Ding ,  Junaida Abu Bakar

发明人： Raj N. Master ,  Mohammad Z. Khan ,  Maria G. Guardado ,  Diong Hing Ding ,  Junaida Abu Bakar

IPC分类号： B23K3102

CPC分类号： B23K1/203 ,  B23K2101/40 ,  H01L2224/16225 ,  H01L2224/73204 ,  H05K3/3436 ,  H05K3/3489

摘要： A method of manufacturing a flip-chip semiconductor device by attaching a semiconductor die to a substrate using solder comprises the steps of applying a no-clean flux to the semiconductor die and the substrate; heating the solder and the flux in a furnace to bond the semiconductor die to the substrate; and underfilling between the semiconductor die and the substrate. While the solder and flux is being heated, a reducing atmosphere in the furnace is being measured to determine the moisture content. When the moisture content exceeds a threshold amount, a signal will be provided. A reflow furnace for practicing the method is also disclosed.

摘要翻译： 通过使用焊料将半导体管芯附着到衬底来制造倒装芯片半导体器件的方法包括以下步骤：向半导体管芯和衬底施加免清洗助焊剂; 在炉中加热焊料和焊剂以将半导体管芯粘合到衬底上; 并且在半导体管芯和衬底之间的底部填充。 当焊料和焊剂被加热时，测量炉中的还原气氛以确定含水量。 当水分含量超过阈值时，将提供信号。 还公开了用于实施该方法的回流炉。

公开(公告)号：US06371310B1

公开(公告)日：2002-04-16

申请号：US09740838

申请日：2000-12-21

申请人： Raj N. Master ,  Mohammad Z. Khan ,  L. K. Teoh

发明人： Raj N. Master ,  Mohammad Z. Khan ,  L. K. Teoh

IPC分类号： A47F700

CPC分类号： H01L21/67333

摘要： A boat is formed with layers comprising substantially aligned holes for safely accommodating land grid array semiconductor packages during assembly. The boat includes a bottom layer with an array of through-holes having a substantially square cross-sectional shape with rounded corners, a middle layer with an array of through-holes having a substantially octagonal cross-sectional shape and a top layer having an array of through-holes having a substantially square cross-sectional shape with notched sides and vertical tabs extending upwardly from the sidewalls of each notched side. The layers may be attached by spot welding or other means.

摘要翻译： 船形成有包括基本上对准的孔的层，用于在组装期间安全地容纳平台阵列半导体封装。 船包括具有基本上具有圆角的基本正方形横截面形状的通孔阵列的底层，具有基本上八边形横截面形状的通孔阵列的中间层和具有阵列的顶层 的通孔具有基本正方形的横截面形状，具有切口侧面和从每个缺口侧的侧壁向上延伸的垂直突出部。 这些层可以通过点焊或其他方式附着。

公开(公告)号：US06258612B1

公开(公告)日：2001-07-10

申请号：US09642832

申请日：2000-08-22

申请人： Raj N. Master ,  Jonathan D. Halderman

发明人： Raj N. Master ,  Jonathan D. Halderman

IPC分类号： H01L2166

CPC分类号： H01L22/20 ,  H01L24/81 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  Y10S33/04 ,  H01L2924/00

摘要： A package assembly is formed by applying flux to a device and/or a substrate and inspecting the applied flux to determine whether the amount applied is within a predetermined range. Embodiments include applying a rosin based flux on a laminate substrate and measuring the thickness of the applied flux with an interferometer.

摘要翻译： 通过将助焊剂施加到装置和/或基底并检查所施加的通量以确定所施加的量是否在预定范围内来形成包装组件。 实施方案包括在层压基板上施加松香基焊剂并用干涉仪测量施加的焊剂的厚度。

公开(公告)号：US6103549A

公开(公告)日：2000-08-15

申请号：US40643

申请日：1998-03-17

申请人： Raj N. Master ,  Orion K. Starr ,  Maria Guardado ,  Mohammad Zubair Khan

发明人： Raj N. Master ,  Orion K. Starr ,  Maria Guardado ,  Mohammad Zubair Khan

IPC分类号： H05K3/34 ,  H01L21/56 ,  H01L21/60 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/563 ,  H01L24/81 ,  H01L2224/13111 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/351

摘要： A method of assembling a substrate and die in a flip chip configuration using a no clean flux. The no clean fluxes have sufficient chemical activity to activate solder bumps contacting bond pads to form reliable solder joints, sufficient tackiness to hold the substrate and die in alignment with the solder bumps contacting the bond pads, and a viscosity to enable a high volume manufacturing process to be used. The no clean fluxes leave a minimal amount of residue during a reflow process that does not interfere with an underfill operation and does not adversely affect the solder joints. The no clean fluxes that can be used for this application are RM1919 from Alpha Metals, Co. and H208 from Indium Company.

摘要翻译： 使用无清洁焊剂以倒装芯片配置组装衬底和管芯的方法。 不干净的焊剂具有足够的化学活性以激活焊料凸点接触焊盘以形成可靠的焊接接头，足够的粘性以保持衬底和管芯与接触焊盘接触的焊料凸块对齐，并且具有使得能够进行大量制造工艺的粘度 要使用的。 不干净的焊剂在回流过程中留下最少量的残留物，其不会妨碍底部填充操作，并且不会不利地影响焊点。 可用于本应用的无清洁助焊剂来自Alpha Metals，Co.的RM1919和Indium Company的H208。