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    Semiconductor device including chip with complementary I/O cells
    21.
    发明授权
    Semiconductor device including chip with complementary I/O cells 有权
    半导体器件包括具有互补I / O单元的芯片

    公开(公告)号：US08581302B2

    公开(公告)日：2013-11-12

    申请号：US13295053

    申请日：2011-11-12

    申请人： Mitsuya Kinoshita ,  Motoo Suwa ,  Akinobu Watanabe ,  Shigezumi Matsui

    发明人： Mitsuya Kinoshita ,  Motoo Suwa ,  Akinobu Watanabe ,  Shigezumi Matsui

    IPC分类号： H01L27/118

    CPC分类号： H01L27/0207 ,  H01L24/02 ,  H01L27/11898 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/14131 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014

    摘要： Signals outputted from an I/O buffer with a parallel drive configuration are stabilized for reliability enhancement. Each I/O cell has a complementary I/O cell that outputs one output signal as a complementary signal made up of a non-inverted signal and an inverted signal. Two I/O cells are coupled in parallel. Output portions of first inverters are coupled together through a first wiring; and output portions of second inverters are coupled together through a second wiring. The first wiring is formed on the lower side of the I/O cells so that it is astride the two I/O cells, and the second wiring is formed above the first wiring so that it is astride the two I/O cells. The wirings are laid out so that the wiring length of the first wiring and the wiring length of the second wiring are substantially equal to each other.

    摘要翻译： 从具有并行驱动器配置的I / O缓冲器输出的信号稳定可靠性提高。 每个I / O单元具有互补I / O单元，其输出一个输出信号作为由非反相信号和反相信号组成的互补信号。 两个I / O单元并联耦合。 第一反相器的输出部分通过第一布线耦合在一起; 并且第二反相器的输出部分通过第二布线耦合在一起。 第一布线形成在I / O单元的下侧，使得它跨越两个I / O单元，并且第二布线形成在第一布线之上，使得它跨越两个I / O单元。 布置布线使得第一布线的布线长度和第二布线的布线长度基本相等。

    SEMICONDUCTOR DEVICE
    22.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120126403A1

    公开(公告)日：2012-05-24

    申请号：US13295053

    申请日：2011-11-12

    申请人： Mitsuya KINOSHITA ,  Motoo Suwa ,  Akinobu Watanabe ,  Shigezumi Matsui

    发明人： Mitsuya KINOSHITA ,  Motoo Suwa ,  Akinobu Watanabe ,  Shigezumi Matsui

    IPC分类号： H01L23/498

    CPC分类号： H01L27/0207 ,  H01L24/02 ,  H01L27/11898 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/14131 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014

    摘要： Signals outputted from an I/O buffer with a parallel drive configuration are stabilized for reliability enhancement. Each I/O cell has a complementary I/O cell that outputs one output signal as a complementary signal made up of a non-inverted signal and an inverted signal. Two I/O cells are coupled in parallel. Output portions of first inverters are coupled together through a first wiring; and output portions of second inverters are coupled together through a second wiring. The first wiring is formed on the lower side of the I/O cells so that it is astride the two I/O cells, and the second wiring is formed above the first wiring so that it is astride the two I/O cells. The wirings are laid out so that the wiring length of the first wiring and the wiring length of the second wiring are substantially equal to each other.

    摘要翻译： 从具有并行驱动器配置的I / O缓冲器输出的信号稳定可靠性提高。 每个I / O单元具有互补I / O单元，其输出一个输出信号作为由非反相信号和反相信号组成的互补信号。 两个I / O单元并联耦合。 第一反相器的输出部分通过第一布线耦合在一起; 并且第二反相器的输出部分通过第二布线耦合在一起。 第一布线形成在I / O单元的下侧，使得它跨越两个I / O单元，并且第二布线形成在第一布线之上，使得它跨越两个I / O单元。 布置布线使得第一布线的布线长度和第二布线的布线长度基本相等。

    Data processor
    25.
    发明授权
    Data processor 有权

    公开(公告)号：US07003763B2

    公开(公告)日：2006-02-21

    申请号：US09985289

    申请日：2001-11-02

    申请人： Ryo Sudo ,  Shigezumi Matsui ,  Yasunori Matsumoto

    发明人： Ryo Sudo ,  Shigezumi Matsui ,  Yasunori Matsumoto

    IPC分类号： G06F9/44

    CPC分类号： G06F11/364

    摘要： A data processor having a debugging aid function capable of monitoring a plurality of kinds of internal buses from the outside and identifying each of the buses monitored is provided. A central processing unit (CPU), a debugging aid module, and other circuit modules are mounted on a semiconductor chip. The debugging aid module selects an information transmitting path in accordance with a trace condition from a plurality of information transmitting paths used for the operation of a central processing unit (CPU) or the like, holds trace information obtained according to the trace condition from the selected information transmitting path together with attribute information of the trace information in a buffer circuit, and outputs the information serially to the outside of the semiconductor chip. A plurality of kinds of internal buses can be monitored on the outside, and each of the buses monitored can be identified. The trace information and its attribute information is output serially from the same external terminal.

    Data processor and data processing system
    26.
    发明授权
    Data processor and data processing system 失效

    公开(公告)号：US07000140B2

    公开(公告)日：2006-02-14

    申请号：US09993704

    申请日：2001-11-27

    申请人： Haruyasu Okubo ,  Atsushi Kiuchi ,  Shigezumi Matsui

    发明人： Haruyasu Okubo ,  Atsushi Kiuchi ,  Shigezumi Matsui

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3237 ,  G06F1/3203 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D50/20

    摘要： This data processor can satisfy both requests of a fast transition from a low power consumption state to an operating state and low power consumption, and a data processor has a program running state, a standby mode, a light standby mode, and a sleep mode. In the sleep mode, the supply of a synchronizing clock signal to a central processing unit (CPU) is stopped and the synchronizing clock signal is supplied to other circuit modules. In the standby mode, the frequency multiplication and frequency operation of a clock pulse generator are suspended and the supply of the synchronizing clock signal to the CPU and other circuit modules is stopped. In the light standby mode, the frequency multiplication and frequency division operation of the clock pulse generator are enabled and the supply of the synchronizing clock signal to the CPU and other circuit modules is stopped. In the light standby mode, the transition of the CPU to an instruction executable state is faster than in the standby mode and the lower power consumption than in the sleep mode is obtained.

    Data processer and data processing system
    28.
    发明授权
    Data processer and data processing system 失效

    公开(公告)号：US06542982B2

    公开(公告)日：2003-04-01

    申请号：US09783551

    申请日：2001-02-15

    申请人： Yasuyuki Murakami ,  Shigezumi Matsui ,  Kunihiko Nishiyama ,  Atsushi Kiuchi ,  Yuichi Takitsune

    发明人： Yasuyuki Murakami ,  Shigezumi Matsui ,  Kunihiko Nishiyama ,  Atsushi Kiuchi ,  Yuichi Takitsune

    IPC分类号： G06F940

    CPC分类号： G06F9/3814 ,  G06F9/3802

    摘要： In order to simplify the instruction prefetch architecture for use with the programs having few loops, and having instructions almost in linear and sequential addresses, the bus controller in accordance with the present invention for controlling the bus in an external memory includes a plurality of instruction buffers, flags each specific to each of instruction buffers, and a buffer controller circuit. The buffer controller circuit may allocate one of specific values that plural lower bits of an instruction address may take to each of the instruction buffers, and prefetch instructions to the instruction buffers each corresponding to a respective addresses designated to by the plural lower bits, from the address following a predetermined fetch address. The constitution for instruction prefetch as above may be implemented in a simpler manner than the controlling structure using address tags of a cache memory or the controlling structure using read-write pointer based on the counter in FIFO buffers.

    Semiconductor integrated circuit
    29.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US07945801B2

    公开(公告)日：2011-05-17

    申请号：US12169853

    申请日：2008-07-09

    申请人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

    发明人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

    IPC分类号： H04L7/00

    CPC分类号： G06F13/4243 ,  G06F13/1689

    摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.

    摘要翻译： 存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。 时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。 存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样 通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。